2019-04-22 |
whitequark | back.verilog: allow stripping the src attribute, for...
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commit | commitdiff | tree |
2019-04-22 |
whitequark | compat.fhdl.specials: fix TSTriple.
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commit | commitdiff | tree |
2019-04-22 |
whitequark | hdl.ir: rework named port handling for Instances.
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commit | commitdiff | tree |
2019-04-21 |
whitequark | Remove examples/tbuf.py.
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commit | commitdiff | tree |
2019-04-21 |
whitequark | hdl.ir: detect elaboratables that are created but not...
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commit | commitdiff | tree |
2019-04-21 |
whitequark | back.rtlil: emit `nmigen.hierarchy` attribute.
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commit | commitdiff | tree |
2019-04-21 |
whitequark | hdl.ast: improve tests for exceptional conditions.
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commit | commitdiff | tree |
2019-04-21 |
whitequark | hdl.ast: accept Signals with identical min/max bounds.
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commit | commitdiff | tree |
2019-04-21 |
whitequark | back.rtlil: only expand legalized values in Array/Part...
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commit | commitdiff | tree |
2019-04-21 |
whitequark | hdl.rec: implement Record.connect.
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commit | commitdiff | tree |
2019-04-20 |
whitequark | back.rtlil: allow record slices on LHS.
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commit | commitdiff | tree |
2019-04-19 |
whitequark | hdl.rec: fix slicing of records.
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commit | commitdiff | tree |
2019-04-18 |
whitequark | hdl.xfrm: handle classes that inherit from Record.
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commit | commitdiff | tree |
2019-04-15 |
whitequark | lib.io: rework TSTriple/Tristate interface to use pin_layout...
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commit | commitdiff | tree |
2019-04-10 |
whitequark | hdl.ast: fix some type checks.
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commit | commitdiff | tree |
2019-04-10 |
whitequark | hdl.xfrm: allow using FragmentTransformer on any elaboratable.
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commit | commitdiff | tree |
2019-04-09 |
whitequark | hdl: remove deprecated get_fragment() and lower() methods.
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commit | commitdiff | tree |
2019-04-03 |
whitequark | hdl.ast: handle a common typo, such as Signal(1, True).
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commit | commitdiff | tree |
2019-03-28 |
whitequark | test_sim: add missing add_process().
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commit | commitdiff | tree |
2019-03-28 |
whitequark | back.rtlil: fix off-by-one in Part legalization.
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commit | commitdiff | tree |
2019-03-25 |
whitequark | hdl.ast: fix typo.
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commit | commitdiff | tree |
2019-03-03 |
whitequark | lib.fifo: register GrayEncoder output before CDC.
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commit | commitdiff | tree |
2019-03-03 |
whitequark | tracer: factor out get_var_name(default=).
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commit | commitdiff | tree |
2019-03-03 |
whitequark | hdl.rec: remove __slots__.
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commit | commitdiff | tree |
2019-02-14 |
whitequark | hdl.ir: raise a more descriptive error on non-elaboratable...
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commit | commitdiff | tree |
2019-01-26 |
whitequark | back.rtlil: accept ast.Const as cell parameter.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | hdl.ast: fix ValueKey for Cat.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat.fhdl.module: fix typo.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat.fhdl.specials: fix __all__ list.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat.genlib.resetsync: add shim for AsyncResetSynchronizer.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat.fifo: fix _FIFOInterface deprecation wrapper.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | lib.cdc: add ResetSynchronizer.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | back.pysim: support async reset.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | back.pysim: give better names to unnamed fragments...
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commit | commitdiff | tree |
2019-01-26 |
whitequark | examples: update for newer API.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | back.rtlil: accept any elaboratable, not just fragments.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat: suppress deprecation warnings that are internal...
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commit | commitdiff | tree |
2019-01-26 |
whitequark | test.compat: reenable tests converting to Verilog.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | compat.sim: fix deprecated stdlib import.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate().
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commit | commitdiff | tree |
2019-01-26 |
whitequark | test.compat: import tests from Migen as appropriate.
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commit | commitdiff | tree |
2019-01-26 |
whitequark | hdl.ast: fix shape calculation for *.
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commit | commitdiff | tree |
2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync...
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commit | commitdiff | tree |
2019-01-22 |
whitequark | lib.fifo: in FIFOInterface.read(), check readable on...
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commit | commitdiff | tree |
2019-01-22 |
whitequark | compat.genlib.fifo: adjust _FIFOInterface shim to not...
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commit | commitdiff | tree |
2019-01-22 |
whitequark | lib.fifo: fix typo in AsyncFIFO documentation.
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commit | commitdiff | tree |
2019-01-21 |
whitequark | lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
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commit | commitdiff | tree |
2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing...
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commit | commitdiff | tree |
2019-01-20 |
whitequark | compat.genlib.cdc: add missing import.
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commit | commitdiff | tree |
2019-01-20 |
whitequark | compat.genlib.cdc: add GrayCounter and GrayDecoder...
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commit | commitdiff | tree |
2019-01-20 |
whitequark | lib.coding: add GrayEncoder and GrayDecoder.
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commit | commitdiff | tree |
2019-01-20 |
whitequark | lib.coding: add width as attribute to all coders.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | lib.fifo: use memory in the FIFO model.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | lib.fifo: use model equivalence to simplify formal...
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commit | commitdiff | tree |
2019-01-19 |
whitequark | hdl.ast: implement shape for modulo operator.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | hdl.ast: add Value.implies.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | hdl.xfrm: mark internal registers used in lowering...
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commit | commitdiff | tree |
2019-01-19 |
whitequark | doc: update COMPAT_SUMMARY.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | fhdl.specials: add compatibility shim for Tristate.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | lib.fifo: fix simulation read/write methods to take...
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commit | commitdiff | tree |
2019-01-19 |
whitequark | compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | lib.fifo: formally verify FIFO contract.
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commit | commitdiff | tree |
2019-01-19 |
whitequark | hdl.ast: give Assert and Assume their own src_loc.
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commit | commitdiff | tree |
2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | lib.fifo: add basic formal specification.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | formal: extract from toplevel module.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer.
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commit | commitdiff | tree |
2019-01-17 |
whitequark | hdl.ast: add Sample.
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commit | commitdiff | tree |
2019-01-16 |
whitequark | lib.fifo: port sync FIFO queues from Migen.
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commit | commitdiff | tree |
2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when tracer...
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commit | commitdiff | tree |
2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals...
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commit | commitdiff | tree |
2019-01-16 |
whitequark | back.rtlil: rename \sig$next to $next$sig.
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commit | commitdiff | tree |
2019-01-16 |
whitequark | Travis: install SymbiYosys and Yices2.
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commit | commitdiff | tree |
2019-01-15 |
whitequark | Unbreak 655d02d5.
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commit | commitdiff | tree |
2019-01-14 |
whitequark | lib.io: pass pin to platform.get_tristate().
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commit | commitdiff | tree |
2019-01-14 |
whitequark | hdl.ir: allow explicitly requesting flattening.
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commit | commitdiff | tree |
2019-01-14 |
whitequark | lib.io: lower to platform-independent tristate buffer.
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commit | commitdiff | tree |
2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS.
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commit | commitdiff | tree |
2019-01-13 |
whitequark | hdl.dsl: cases wider than switch test value are unreachable.
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commit | commitdiff | tree |
2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch...
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commit | commitdiff | tree |
2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals.
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commit | commitdiff | tree |
2019-01-13 |
whitequark | back.verilog: better error message if Yosys is not...
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commit | commitdiff | tree |
2019-01-08 |
whitequark | back.verilog: remove undriven check.
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commit | commitdiff | tree |
2019-01-02 |
whitequark | hdl.ast: allow slicing [n:n] into n-bit value.
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commit | commitdiff | tree |
2019-01-02 |
whitequark | back.rtlil: translate empty slices correctly.
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commit | commitdiff | tree |
2019-01-01 |
whitequark | hdl.ast: experimentally add Value._as_const.
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commit | commitdiff | tree |
2019-01-01 |
whitequark | back.rtlil: fix typo.
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commit | commitdiff | tree |
2019-01-01 |
whitequark | hdl.rec: include record name in error message.
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commit | commitdiff | tree |
2019-01-01 |
whitequark | hdl.rec: use a helpful error on unknown field reference.
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commit | commitdiff | tree |
2019-01-01 |
whitequark | hdl.mem: add DummyPort, for testing and verification.
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commit | commitdiff | tree |
2018-12-31 |
whitequark | back.rtlil: match shape of Array elements to ArrayProxy...
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commit | commitdiff | tree |
2018-12-31 |
whitequark | back.rtlil: fix typo.
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commit | commitdiff | tree |
2018-12-29 |
whitequark | lib.cdc: fix tests to actually run.
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commit | commitdiff | tree |
2018-12-29 |
whitequark | back.pysim: warn if simulation is not run.
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commit | commitdiff | tree |
2018-12-28 |
whitequark | hdl.rec: add basic record support.
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commit | commitdiff | tree |
2018-12-28 |
whitequark | tracer: factor out get_src_loc().
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commit | commitdiff | tree |
2018-12-27 |
whitequark | lib.coding: fix tests to actually run, and fix code...
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commit | commitdiff | tree |
2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing().
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commit | commitdiff | tree |
next |