nmigen.git
2019-07-02 Alain Péteutbuild.plat: add iter_extra_files method.
2019-07-02 whitequarkback.rtlil: emit \sig$next wires instead of \$next...
2019-07-02 whitequarkback.rtlil: do not emit $next wires for comb signals.
2019-07-02 whitequarkhdl.rec: implement slicing by component names.
2019-07-02 whitequarkhdl.rec: implement Record.like.
2019-07-02 Alain Péteutvendor.xilinx_7series: read extra .xdc files.
2019-07-01 whitequarkhdl.mem: use read_port(domain="comb") for asynchronous...
2019-07-01 whitequarkback.rtlil: fix Array regression in 32446831.
2019-06-28 whitequarkback.pysim: create unique ResetSynchronizer internal...
2019-06-28 whitequarkback.pysim: override ResetSynchronizer implementation.
2019-06-28 whitequarklib.cdc: avoid interior clock domains in ResetSynchronizer.
2019-06-28 whitequarklib.cdc: eliminate no_retiming attributes.
2019-06-28 whitequarkvendor.lattice_ice40: fix instance of negedge FF due...
2019-06-28 Alain Péteutbuild.plat: fix dedent overrides.
2019-06-28 whitequarkREADME: tone down the instability warning to reflect...
2019-06-28 whitequarkhdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case...
2019-06-28 whitequarkhdl.ir, back.rtlil: allow specifying attributes on...
2019-06-27 whitequarkexamples: add concise UART example.
2019-06-26 whitequarkback.pysim: fix scope screwup.
2019-06-25 whitequarkcompat.fhdl.structure: fix typo.
2019-06-25 whitequarkcompat.fhdl.structure: simplify handling of default...
2019-06-25 whitequarkhdl.{ast,dst}: directly represent RTLIL default case.
2019-06-25 whitequarkvendor.xilinx_{spartan6,7series}: speedgrade→speed.
2019-06-25 whitequarkvendor.lattice_ecp5: implement.
2019-06-24 Sebastien BourdeauducqREADME: update nMigen libs paragraph
2019-06-24 Sebastien BourdeauducqREADME: add clarification about HLS
2019-06-19 whitequarkvendor.lattice_ice40: use different --package for 4k...
2019-06-17 Jean-François... vendor.xilinx_7series: fix IOB packing.
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explic...
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: cleanup. NFC.
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: connect FCDE and...
2019-06-16 Alain Péteutbuild.plat: dedent overrides.
2019-06-14 whitequarkvendor.lattice_ice40: never place an inverter on global...
2019-06-13 Jean-François... vendor.xilinx_7series: implement inverters.
2019-06-13 Jean-François... vendor.xilinx_spartan6: implement DDR I/O buffers and...
2019-06-13 whitequarkcompat.fhdl.structure: fix Case().makedefault().
2019-06-13 whitequarkcompat.fhdl.structure: always order default case as...
2019-06-13 whitequarkhdl.ast: tighten assertion in Switch().
2019-06-12 whitequarkSimplify code by using Signal.like(name_suffix=".....
2019-06-12 whitequarkhdl.ast: add name_suffix=".." option to Signal.like().
2019-06-12 Jean-François... vendor.xilinx_7series: implement DDR I/O buffers.
2019-06-12 whitequarkvendor.lattice_ice40: fix typo.
2019-06-12 whitequarkbuild.{dsl,res,plat}: add PinsN and DiffPairsN.
2019-06-11 whitequarkhdl.ast: implement values with custom lowering.
2019-06-11 whitequarkback.pysim: check for a clock being added twice.
2019-06-11 whitequarkback.rtlil: mask memory init values.
2019-06-11 whitequarkhdl.mem: coerce memory init values to integers.
2019-06-09 Simon Kirkbylib.cdc: fix typo.
2019-06-07 Jean-François... vendor.xilinx_spartan6: implement.
2019-06-07 Jean-François... vendor.xilinx_7series: fix typos.
2019-06-06 whitequarkbuild.dsl: fix precondition check in Pins.
2019-06-06 Jean-François... vendor.xilinx_7series: implement.
2019-06-05 whitequarkbuild.res: allow querying frequency of a previously...
2019-06-05 whitequarkbuild.{dsl,res,plat}: apply clock constraints to signal...
2019-06-05 whitequarkbuild.dsl: replace extras= with Attrs().
2019-06-05 whitequarkTypos and style fixes. NFC.
2019-06-04 whitequarkvendor.lattice_ice40: normalize device names.
2019-06-04 whitequarkhdl.ir: rephrase elaboratable warning to not look like...
2019-06-04 whitequarkcompat.fhdl.module: silence "unused elaboratable" warnings.
2019-06-04 whitequarkcompat.fhdl.specials: fix platform lowering for TSTripl...
2019-06-04 whitequarkcompat.fhdl.specials: fix platform lowering.
2019-06-04 whitequarkcompat.fhdl.module: implement some TODO'd deprecation...
2019-06-04 whitequarkbuild.run: fix product extraction to work on Windows.
2019-06-04 whitequarkbuild.plat: hide executed commands in quiet builds...
2019-06-04 whitequarkbuild.plat: allow (easily) overriding with an empty...
2019-06-04 whitequarkcompat.fhdl.module: CompatModule should be elaboratable.
2019-06-04 whitequarkbuild.res: use ConstraintError iff a constraint invaria...
2019-06-04 whitequarkhdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}.
2019-06-04 whitequarkvendor.board: split off into nmigen-boards package.
2019-06-04 whitequarkbuild.run: simplify using build products locally, e...
2019-06-04 whitequarkbuild.res: simplify emission of port constraints on...
2019-06-04 whitequarkClean up imports.
2019-06-04 whitequarkbuild.run: extract from build.plat.
2019-06-04 whitequarkvendor.board.tinyfpga_bx: clk16 pin does not have a...
2019-06-04 whitequarkvendor.board.tinyfpga_bx: fix typo.
2019-06-03 whitequarkvendor.conn.pmod: implement.
2019-06-03 whitequarkexamples: reorganize into examples/basic and examples...
2019-06-03 whitequarkvendor.board: extract package.
2019-06-03 whitequarkvendor.tinyfpga_bx: add connectors.
2019-06-03 whitequarkvendor.icestick: add connectors.
2019-06-03 whitequarkvendor.ice40_hx1k_blink_evn: add (some) connectors.
2019-06-03 whitequarkbuild.{plat,res}: add support for connectors.
2019-06-03 whitequarkbuild.dsl: add support for connectors.
2019-06-03 whitequarkcompat.fhdl.specials: TSTriple is not an elaboratable.
2019-06-03 whitequarkvendor.fpga.lattice_ice40: implement differential outpu...
2019-06-03 whitequarkvendor.fpga.lattice_ice40: implement differential input...
2019-06-03 whitequarkvendor.fpga.lattice_ice40: allow instantiating SB_GB_IO...
2019-06-03 whitequarkvendor.fpga.lattice_ice40: implement SDR and DDR I...
2019-06-03 whitequarklib.io: add i_clk and o_clk to pin layout with xdr>=1.
2019-06-03 whitequarkhdl.rec: unbreak hasattr(rec, ...).
2019-06-03 whitequarkbuild.{dsl,plat,res}: allow dir="oe".
2019-06-03 whitequarklib.io: allow dir="oe".
2019-06-03 whitequarkbuild.{res,plat}: use xdr=0 as default, not xdr=1.
2019-06-03 whitequarkbuild.res: allow requesting raw ports, with dir="-".
2019-06-03 whitequarklib.io: allow Pin(xdr=0), representing a combinatorial...
2019-06-03 whitequarkvendor.fpga.lattice_ice40: enable SystemVerilog when...
2019-06-03 whitequarkbuild.res: if not specified, request resource #0.
2019-06-03 whitequarkvendor.fpga.lattice_ice40: instantiate SB_IO and apply...
2019-06-03 whitequarkhdl.ir: accept LHS signals like slices as Instance...
2019-06-03 whitequarkhdl.dsl: allow adding submodules with computed name...
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