riscv-isa-sim.git
2017-11-04 Andrew WatermanFix disassembly of c.li 0
2017-11-03 Palmer DabbeltMerge pull request #151 from riscv/htif_dts
2017-11-03 Palmer DabbeltPut HTIF in the device tree
2017-11-03 Andrew WatermanMask medeleg correctly
2017-11-02 Andrew WatermanDon't permit delegation of interrupts that M-mode shoul...
2017-10-20 Andrew WatermanFix commit-log for Q extension, and for RV32 (#143)
2017-10-19 Evan CoxFix bus_t bug with devices at 0x0
2017-10-19 Andrew WatermanFix implementation of FMIN/FMAX NaN case
2017-10-15 jarInclude math.h for NAN (#137)
2017-10-11 Andrew WatermanMerge pull request #129 from riscv/q-extension
2017-09-28 Andrew WatermanImplement Q extension
2017-09-25 Tim NewsomeMerge pull request #128 from riscv/reset
2017-09-25 Andrew WatermanUpdate SoftFloat
2017-09-21 Tim NewsomeActually let hartreset be set.
2017-09-21 Tim NewsomeFix debug reset.
2017-09-21 Tim NewsomeFix corner case in repeated execution (#127)
2017-09-21 Tim NewsomeFix comment typo. (#126)
2017-09-12 Tim NewsomeMerge pull request #123 from riscv/debug_interrupts
2017-09-12 Tim NewsomeDon't take interrupts while in Debug Mode.
2017-08-28 Tim NewsomeMerge pull request #121 from riscv/debug_store
2017-08-28 Tim NewsomeAdd a nice debug printf for debug_module_t::store
2017-08-11 Tim NewsomeMerge pull request #119 from riscv/quiet
2017-08-11 Tim NewsomeTurn off debug module debug printfs.
2017-08-10 Palmer DabbeltCorrect c.li and c.lui disassembly (#118)
2017-08-10 Tim NewsomeMerge pull request #117 from riscv/multicore_debug
2017-08-07 Tim NewsomeFix multicore debug.
2017-06-30 Andrew WatermanRemove reference to H-mode in ECALL
2017-06-14 Palmer DabbeltMerge pull request #113 from riscv/debug_readme
2017-06-14 Tim NewsomeSupport 64-bit start PCs in reset vector.
2017-06-09 Tim NewsomeUpdate README to use --rbb-port
2017-06-09 Tim NewsomeMerge pull request #112 from riscv/autoexecwrite
2017-06-09 Tim NewsomeReturn success on writes to abstractauto
2017-06-08 Tim NewsomeMerge pull request #110 from riscv/debug_rom_build
2017-06-08 Tim NewsomeMerge pull request #111 from riscv/dtm_reset_error
2017-06-08 Tim NewsomeReset to "success" instead of "error."
2017-06-08 Tim Newsome`make clean && make` works again in debug_rom
2017-06-07 Andrew WatermanForbid S-mode execution from user memory
2017-06-05 Palmer DabbeltMerge pull request #108 from riscv/dtc-error
2017-06-05 Andrew WatermanConfigure should fail if device-tree-compiler is not...
2017-05-25 Andrew WatermanminNum -> minimumNumber
2017-05-23 Palmer DabbeltMerge pull request #104 from riscv/disable-werror
2017-05-23 Palmer DabbeltDisable -Werror when building
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-05-16 Palmer DabbeltBetter error message when doing DMI operations and...
2017-05-15 Megan Wachsdebug: whitespace errors
2017-05-15 Megan WachsMerge branch 'debug-0.13' into HEAD
2017-05-14 Andrew WatermanMake C.LI/C.LUI trapping behavior match spec
2017-05-05 Andrew WatermanUXL=SXL=MXL
2017-05-05 Andrew WatermanTrap superpage PTEs when PPN LSBs are set
2017-05-03 Kito ChengAdd missing include for devices.h
2017-05-01 Andrew WatermanFix segfault when accessing bad memory addresses
2017-05-01 Andrew WatermanSet default entry point from ELF
2017-05-01 Andrew WatermanAdd option to set start pc
2017-05-01 Andrew WatermanSupport more flexible main memory allocation
2017-05-01 Andrew WatermanStore both host & target address in soft TLB
2017-04-26 Palmer DabbeltMerge pull request #96 from riscv/ndmreset
2017-04-26 Palmer DabbeltRemove a debugging printf
2017-04-26 Palmer DabbeltDon't spin on the remote bitbang reads
2017-04-26 Palmer DabbeltHandle abstractcs.busy
2017-04-26 Palmer DabbeltHave ndmreset reset the processor
2017-04-25 Andrew WatermanFMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
2017-04-25 Andrew WatermanRemove hret instruction
2017-04-24 Palmer DabbeltMerge pull request #94 from riscv/commitlog
2017-04-19 Palmer DabbeltFix builds with "--enable-commitlog"
2017-04-18 Megan Wachsdebug: move remote_bitbang into riscv
2017-04-18 Megan Wachsdebug: Remove duplicate remote_bitbang file
2017-04-18 Megan Wachsdebug: Able to successfully examine a single hart.
2017-04-18 Megan Wachsdebug: Use Debug-Module specific constants instead...
2017-04-18 Megan Wachsdebug: Add fence and fence.i to ensure Debug RAM is...
2017-04-18 Megan Wachsdebug: Checkpoint which somewhat works with OpenOCD...
2017-04-18 Megan Wachsdebug: move the debug_rom defines to a seperate file
2017-04-18 Megan Wachsdebug: Use more unique debug ROM names
2017-04-18 Megan Wachsdebug: Use a more practical debug ROM
2017-04-18 Megan Wachsdebug: Move things around, but addresses now conflict...
2017-04-17 Megan Wachsdebug: consider COMMAND.transfer bit, and implment...
2017-04-17 Megan Wachsdebug: Compiles again with new debug_defines.h file...
2017-04-17 Megan Wachsdebug: bump the debug_defines to match spec
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-11 Andrew WatermanImplement new FP encoding
2017-04-08 Andrew WatermanImplement vectored interrupt proposal
2017-04-06 Andrew WatermanAdd --enable-misaligned option for misaligned ld/st...
2017-04-01 Yunsup Leeupdate encoding.h to get PMP updates
2017-04-01 Andrew WatermanUpdate LICENSE copyright date
2017-03-30 Wesley W. Terpstrafdt: move interrupt controller into its own node
2017-03-28 Andrew WatermanSet badaddr=0 on illegal instruction traps
2017-03-28 Andrew WatermanOn EBREAK, set badaddr to pc
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2017-03-25 Andrew WatermanDefault to 2 GiB of memory
2017-03-23 Andrew WatermanRequire little-endian host
2017-03-22 Wesley W. Terpstrariscv: replace rtc device with a real clint implementation
2017-03-22 Wesley W. Terpstrasim: declare cores as interrupt-controllers for clint
2017-03-21 Wesley W. Terpstrabootrom: set a0 to hartid and a1 to dtb before boot
2017-03-21 Wesley W. Terpstraconfigstring: rename variables to dts
2017-03-21 Wesley W. Terpstrariscv: remove dependency on num_cores
2017-03-21 Wesley W. Terpstrabootrom: include compiled dtb
2017-03-21 Wesley W. Terpstrasim: create DTS instead of config string
2017-03-21 Wesley W. Terpstrasim: define emulated CPU clock rate to be 1GHz
2017-03-21 Wesley W. Terpstraautoconf: put location of 'dtc' into config.h
2017-03-21 Palmer Dabbeltspec bump
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