litex.git
2020-08-04 Florent Kermarrecsetup: add litex_json2dts to console_scripts.
2020-08-04 enjoy-digitalMerge pull request #620 from antmicro/add_litex_json2dts
2020-08-04 Florent Kermarrecbuild/sim/config: add default_clk/default_clk_freq...
2020-08-04 Florent Kermarrecbuild/sim: use json_object_get_int64 instead of json_ob...
2020-08-04 enjoy-digitalMerge pull request #619 from antmicro/jboc/sim-clocker
2020-08-04 Mateusz Holenkojson2dts: Add Linux DT generation script
2020-08-04 Jędrzej Boczarbuild/sim: improve timebase calculation (strict checks...
2020-08-04 Florent Kermarreccores/uart: add txempty/rxfull CSRs.
2020-08-04 Florent Kermarrectools/litex_server: enable read_merger with CommUDP.
2020-08-04 Florent Kermarrectest: specify wishbone adr_width on AXI(Lite)<-->Wishbo...
2020-08-04 enjoy-digitalMerge pull request #617 from gsomlo/gls_rocket_dma
2020-08-03 Gabriel Somlodebug: make CI print offending values
2020-08-03 Gabriel Somloliblitesdcard/sdcard: (temporarily) slow down SDCARD_CL...
2020-08-03 Gabriel Somlocores/cpu/rocket: expose slave port for DMA
2020-08-03 Gabriel Somlointegration/soc: make DMA slave region cover (at least...
2020-08-03 Gabriel Somlointerconnect/wishbone: increase WB address width to 31
2020-08-03 Gabriel Somlosoc/interconnect/axi: add Wishbone2AXI converter
2020-08-03 Florent Kermarreccores/gpio: add support for Record on GPIOOut, GPIOIn...
2020-08-03 Jędrzej Boczarbuild/sim: allow for arbitrary clocks generation using...
2020-08-03 Jędrzej Boczarbuild/sim: use a real timebase in the simulation
2020-08-03 enjoy-digitalMerge pull request #615 from pepijndevos/openfpgaloader
2020-08-01 Pepijn de Vosremove debugging
2020-08-01 Pepijn de Vosadd openFPGAloader programmer
2020-07-31 Florent Kermarreccpu/vexriscv/core: use variant name as human_name.
2020-07-31 Florent Kermarreccpu/vexriscv/system.h: provide empty flush_cpu_i/dcache...
2020-07-30 Florent Kermarreccpu/zynq7000: set csr map to 0x00000000.
2020-07-30 enjoy-digitalMerge pull request #611 from antmicro/jboc/axi-lite
2020-07-30 Florent Kermarrectools/litex_server/read_merger: review/simplify a bit.
2020-07-30 enjoy-digitalMerge pull request #605 from cklarhorst/feature-uart...
2020-07-30 Jędrzej Boczarsoc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 Florent Kermarreccpu/blackparrot: minor cleanups, add sim variant (since...
2020-07-29 enjoy-digitalMerge pull request #610 from Dolu1990/vexriscv_smp
2020-07-29 Dolu1990soc/cores/cpu/vexriscv_smp enable dynamic litedram...
2020-07-29 Dolu1990Merge branch 'master' into vexriscv_smp
2020-07-29 Florent Kermarrecintegration/soc/add_sdram: allow the CPU to add the...
2020-07-29 Florent Kermarreccores/cpu/rocket: add use_memory_bus parameter to easil...
2020-07-28 Dolu1990Merge branch 'master' into vexriscv_smp
2020-07-28 Dolu1990soc/cores/cpu/vexriscv_smp config update
2020-07-28 Florent KermarrecCHANGES: update.
2020-07-28 Florent Kermarreccpu/vexriscv_smp: move litedram import, remove os.path...
2020-07-28 Florent Kermarreclitex_setup: fix vexriscv-smp repository.
2020-07-28 enjoy-digitalMerge pull request #607 from Dolu1990/vexriscv_smp
2020-07-28 Dolu1990soc/cores/cpu/vexriscv_smp integration
2020-07-28 Florent Kermarrecliblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
2020-07-27 Florent Kermarrecintegration/soc/etherbone: expose ethcore (useful to...
2020-07-27 Florent Kermarrecintegration/soc: fix dma_bus typo.
2020-07-26 Christian KlarhorstMerge sequential reads for the UART litex_server backend
2020-07-24 Florent Kermarrectargets: keep in sync with litex-boards.
2020-07-24 enjoy-digitalMerge pull request #604 from antmicro/jboc/axi-lite
2020-07-24 Jędrzej Boczarsoc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 Sean CrossMerge pull request #603 from enjoy-digital/socdoc-exten...
2020-07-24 Sean Crossdoc: socdoc: document new `sphinx_extra_config` parameter
2020-07-24 enjoy-digitalMerge pull request #602 from enjoy-digital/socdoc-exten...
2020-07-24 Sean Crosslitex: add `sphinx_extra_config` to `generate_docs()`
2020-07-24 Sean Crossdoc: socdoc: document `sphinx_extensions` parameter
2020-07-24 Jędrzej Boczarsoc/interconnect/axi: separate AXI Lite converter channels
2020-07-23 Florent KermarrecCHANGES: update.
2020-07-23 Florent Kermarreccore/cpu: integrate Zynq as a classical CPU (Zynq7000...
2020-07-22 Florent Kermarrecliblitesdcard/sdcard: use max divider of 256 (128 was...
2020-07-22 Florent KermarrecCHANGES: update.
2020-07-22 enjoy-digitalMerge pull request #600 from antmicro/jboc/axi-lite
2020-07-22 Florent Kermarrecsoc: add initial DMA bus support (optionally provided...
2020-07-22 Jędrzej Boczartest/axi: move all AXI Lite tests to separate file
2020-07-22 Jędrzej Boczarsoc/integration: use AXILiteSRAM when using bus_standar...
2020-07-22 Jędrzej Boczartest/axi: add crossbar stress tests
2020-07-22 Jędrzej Boczarsoc/integration: add bus standard parser arguments
2020-07-22 Jędrzej Boczarsoc/interconnect/axi: improve Timeout module and test...
2020-07-22 Jędrzej Boczartest/axi: add shared AXI Lite interconnect tests
2020-07-22 Jędrzej Boczarsoc/interconnect/axi: implement AXI Lite decoder
2020-07-22 Jędrzej Boczarsoc/interconnect/axi: lock AXILiteArbiter until all...
2020-07-22 Jędrzej Boczartest/test_axi: add AXI Lite interconnect arbiter tests
2020-07-22 Jędrzej Boczarsocinterconnect/axi: interconnect shared sketch
2020-07-22 Jędrzej Boczarsoc/interconnect/axi: point-to-point interconnect and...
2020-07-22 Jędrzej Boczarsoc/integration: choose interconnect based on bus standard
2020-07-22 Jędrzej Boczarsoc/integration: add axi-lite standard to SoCBusHandler
2020-07-22 enjoy-digitalMerge pull request #599 from antmicro/gen-mmcm-pr
2020-07-22 Piotr Binkowskilitex-gen: add mmcm core
2020-07-22 Florent Kermarrecboards: keep in sync with litex-boards.
2020-07-21 Florent Kermarrecsoc/integration/add_sdcard: add direct connection to...
2020-07-21 Florent Kermarreccpu/vexriscv/system.h: update flush_cpu_dcache.
2020-07-21 Florent Kermarrecinterconnect/wishbone: add minimal UpConverter.
2020-07-20 enjoy-digitalMerge pull request #597 from antmicro/jboc/litex-builde...
2020-07-20 enjoy-digitalMerge pull request #595 from betrusted-io/master
2020-07-20 enjoy-digitalMerge pull request #598 from sergachev/master
2020-07-20 Ilia Sergachevinterconnect/csr_bus: fix paged access warning
2020-07-20 Jędrzej Boczarfix/Vivado: don't instantiate wishbone.Converter in...
2020-07-20 Florent Kermarrecsoftware/liblitesdcard/spisdcard: remove optimization...
2020-07-20 Florent Kermarrecsoc/cores/spi/SPIMaster: rewrite/simplify.
2020-07-18 bunniewire up missing register bits.
2020-07-17 Florent Kermarrecliblitesdcard/spisdcard: update comments.
2020-07-17 Florent Kermarrecsoc/cores/spi: make sure done and miso are synchronous.
2020-07-17 Florent Kermarrecspisdcard: revert to 8-bit SPI, optimize spisdcardrecei...
2020-07-17 Florent Kermarrecsoc/cores/spi: make sure miso is stable during xfer.
2020-07-16 Florent Kermarrecbios/boot: add bootargs support on netboot/sdcardboot...
2020-07-16 enjoy-digitalMerge pull request #594 from antmicro/jboc/axi-lite
2020-07-16 Jędrzej Boczarsoc/interconnect/axi: propagate response errors in...
2020-07-16 Jędrzej Boczarsoc/interconnect/axi: implement AXILite down-converter
2020-07-16 enjoy-digitalMerge pull request #593 from antmicro/jboc/axi-lite
2020-07-16 Jędrzej Boczarsoc/integration: revert `bus` argument for add_ram...
2020-07-15 Jędrzej Boczarsoc/integration: use AXILiteConverter (dummy implementa...
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