riscv-isa-sim.git
2011-11-12 Your NameRemove dependence on binutils
2011-11-11 Andrew WatermanUse new compiler toolchain's disassembler
2011-11-11 Andrew WatermanChanged MFTX to use rs1 for its source
2011-11-11 Andrew WatermanChanged supervisor mode
2011-11-01 Andrew WatermanFixed tight coupling of host and target page size
2011-10-27 Andrew Watermanchanged page size to 8KB
2011-10-19 Yunsup LeeMerge branch 'master' of github.com:ucb-bar/riscv-isa-sim
2011-10-19 Yunsup Leefix vf
2011-10-19 Yunsup Leeyunsup made this fix..ask him
2011-08-18 Andrew Watermandon't forget to commit configure after autoconf!
2011-07-13 Rimas Avizienisadded #include <stdlib.h> to get rid of errors building...
2011-07-08 Rimas Avizienisbugfix to riscv.ac
2011-07-08 Rimas Avizienisfixes to make disassembly work under macos (with macpor...
2011-06-27 Andrew WatermanBuilds and runs on Mac OS 10.6.7
2011-06-20 Andrew Watermanpost-repo-split cleanup
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
2011-06-12 Andrew Waterman[xcc] tlb now stores host addresses
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[xcc] fix configure scripts
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
2011-06-06 Andrew Waterman[sim] fix writeback after ipi clearing
2011-06-05 Andrew Waterman[sim] add ability to clear IPIs
2011-06-01 Andrew Waterman[sim] fault on failed addr translations
2011-05-31 Andrew Waterman[sim] minor sim cleanup
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-23 Andrew Waterman[sim,xcc] add rdcycle/rdtime/rdinstret
2011-05-19 Andrew Waterman[sim] more fp<->int fixes
2011-05-19 Andrew Waterman[sim] more fp conversion bugs fixed
2011-05-19 Yunsup Lee[sim] change default hwvl
2011-05-19 Yunsup Lee[sim] vlen calc reflects the hardware
2011-05-18 Andrew Waterman[sim] fixed fcvt rounding bugs
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support
2011-05-16 Yunsup Lee[sim,xcc] change cond. mov inst format, add implementation
2011-05-16 Yunsup Lee[opcodes,pk,sim,xcc] resolve a conflict
2011-05-16 Yunsup Lee[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec...
2011-05-14 Andrew Waterman[sim] initial support for virtual memory
2011-05-14 Andrew Waterman[sim] stubs for perfctr instructions
2011-05-13 Andrew Watermantweaked encoding of rdcycle & cousins
2011-05-06 Andrew Waterman[sim] fixed building sim without cache simulators
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-25 Andrew Waterman[xcc,sim,opcodes] added c.addiw
2011-04-24 Andrew Waterman[xcc,sim,opcodes] added more RVC instructions
2011-04-24 Andrew Waterman[sim] fixed divw/remw crashing simulator
2011-04-19 Andrew Waterman[xcc,sim] rv64 'w' instruction semantics changed
2011-04-19 Andrew Waterman[xcc,sim,opcodes] added rvc conditional branches
2011-04-17 Andrew Waterman[sim] removed undefined behavior for non-canonical...
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] fixed jalr immediate bug
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-13 Andrew Waterman[xcc,pk,sim] added privileged cflush instruction
2011-04-13 Andrew Waterman[xcc,sim] fixed RM field
2011-04-12 Andrew Waterman[xcc,sim] rvc loads and stores
2011-04-12 Andrew Waterman[sim,pk] fixed minor pk bugs and trap codes
2011-04-12 Andrew Waterman[sim] fixed FSR exception field bug
2011-04-12 Andrew Waterman[xcc,sim,opcodes] more rvc instructions and bug fixes
2011-04-10 Yunsup Lee[sim] add disable option for vector
2011-04-10 Yunsup Lee[sim] set SR_EV for uts
2011-04-10 Yunsup Lee[sim] add vector traps to vector instructions
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-04-10 Andrew Waterman[xcc, sim] added rvc insn c.li; misc fixes
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-04-10 Andrew Waterman[xcc,pk,sim,opcodes] added first RVC instruction
2011-04-08 Andrew Waterman[sim] fixed multiply-high in rv32
2011-04-07 Andrew Waterman[pk,sim] fixed parse-opcodes bug
2011-04-07 Yunsup Lee[opcodes,pk,sim,xcc] fix utidx - add rd
2011-04-05 Yunsup Lee[opcodes,pk,sim,xcc] fix vector mem instruction format...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add leftover vector instructions...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add vector mem instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add stop,utidx instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add fence instructions for vector...
2011-03-30 Andrew Waterman[xcc] fixed bug in amo{maxu,minu}.w
2011-03-26 Andrew Waterman[opcodes] minor opcode changes
2011-03-26 Andrew Waterman[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-03-18 Andrew Waterman[sim] LWU now illegal in RV32
2011-03-01 Andrew Waterman[xcc,sim] branches are pc-relative (not pc+4) again
2011-02-15 Andrew Waterman[xcc,opcodes,pk,sim] krste's re-renaming spree
2011-02-15 Andrew Waterman[xcc,sim,opcodes] removed mtflh/mffl/mffh
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-02-02 Andrew Waterman[sim,xcc,opcodes] added back mtflh.d
2011-02-02 Andrew Waterman[opcodes,pk,sim,xcc] synci now bombs whole icache
2011-02-02 Andrew Waterman[xcc,opcodes,pk,sim] cleanup to FP ISA
2011-02-02 Andrew Waterman[sim] added nearest/ties to max magnitude rounding...
2011-01-27 Andrew Waterman[sim] changed divide-by-0 semantics
2011-01-26 Andrew Waterman[sim,opcodes] add mulhsu instruction
2011-01-26 Andrew Waterman[opcodes,pk,sim,xcc] great renumbering of 2011, part...
2011-01-21 Andrew Waterman[sim, pk, xcc, opcodes] great instruction renaming...
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2011-01-17 Andrew Waterman[opcodes, pk, sim, xcc] removed nor, normalized macros...
2011-01-12 Andrew Waterman[sim] fix jalr bug
2011-01-04 Yunsup Lee[opcodes,pk,sim,xcc] flip fields to favor little endian
2010-12-27 Andrew Waterman[sim] fixed some compiler warnings
2010-12-27 Andrew Waterman[sim] cleaned up handling of link register
2010-11-22 Andrew Waterman[sim] handle integer division overflow
next