Merge pull request #56 from riscv/config
[riscv-tests.git] / debug / targets / RISC-V /
drwxr-xr-x   ..
-rw-r--r-- 478 spike32.cfg
-rwxr-xr-x 683 spike32.lds
-rw-r--r-- 253 spike32.py
-rw-r--r-- 478 spike64.cfg
-rwxr-xr-x 544 spike64.lds
-rw-r--r-- 255 spike64.py