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rename JTAG port in adder test experiments10_verilog (success compile)
[soclayout.git]
/
experiments10_verilog
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drwxr-xr-x
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932
Makefile
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1805
add.py
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coriolis2
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-rw-r--r--
4011
doDesign.py
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lrwxrwxrwx
11
mksym.sh
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../mksym.sh
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netlists.txt
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projects / soclayout.git / tree