projects / soclayout.git / tree
? search:
summary | shortlog | log | commit | commitdiff | tree
history | HEAD
back to "working" verilog add
[soclayout.git] / experiments10_verilog /
drwxr-xr-x   ..
-rwxr-xr-x 932 Makefile blob | history | raw
-rw-r--r-- 1785 add.py blob | history | raw
drwxr-xr-x - coriolis2 tree | history
-rw-r--r-- 3971 doDesign.py blob | history | raw
lrwxrwxrwx 11 mksym.sh -> ../mksym.sh blob | history | raw
-rw-r--r-- 29 netlists.txt blob | history | raw