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Made regs 32-bit word aligned to match the rest of the system
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
drwxr-xr-x
..
-rw-r--r--
17546
I2C.scala
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-rw-r--r--
529
I2CCtrlRegs.scala
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-rw-r--r--
892
I2CPeriphery.scala
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-rw-r--r--
813
I2CPins.scala
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