up the delay-time on ddr3 reset, put loop around dram init just for fun
[ls2.git] / verilator /
drwxr-xr-x   ..
-rw-r--r-- 1414 microwatt-verilator.cpp
-rw-r--r-- 4758 uart-verilator.c
-rw-r--r-- 912 uart-verilator.h