From: Luke Kenneth Casson Leighton Date: Tue, 4 Dec 2018 18:45:18 +0000 (+0000) Subject: reword X-Git-Url: https://git.libre-soc.org/?p=crowdsupply.git;a=commitdiff_plain;h=2998bec348f5f950c8ada342a45965406c9b9723 reword --- diff --git a/updates/003_2018dec04_microarchitecture.mdwn b/updates/003_2018dec04_microarchitecture.mdwn index 55bae1d..64487a7 100644 --- a/updates/003_2018dec04_microarchitecture.mdwn +++ b/updates/003_2018dec04_microarchitecture.mdwn @@ -53,13 +53,11 @@ does not even make it into the instruction queue, leaving it free for use by following instructions, even in the same cycle, and even if the operation is totally different. Thus, unlike in a traditional vectore architecture, ALUs may be occupied by elements from -other "Lanes", because of the pre-existing decoupling between the multi-issue -instruction queue and the ALUs. +other "Lanes", because the pre-existing decoupling between the multi-issue +instruction queue and the ALUs is efficiently leveraged. Simple! -[[reorder_buffer.jpg]] - There are many other benefits to a multi-issue microarchitecture, and these are being discussed [here](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-December/000198.html) @@ -73,6 +71,8 @@ to hit a speed wall. That in particular means that, firstly, it's extremely commonly taught in Universities, and, secondly, patents on the algorithm have long since expired. +[[reorder_buffer.jpg]] + Also, there are both memory hazards and register hazards that a Reorder Buffer augmented Tomasulo algorithm takes care of, whilst also allowing for branch prediction and really simple roll-back, preservation of @@ -84,7 +84,7 @@ extend the Reorder Buffer tags to accomodate SIMD-style characteristics. We also may need to have simple Branch Prediction, because some of the loops in [Kazan](https://salsa.debian.org/Kazan-team/kazan/) are particularly tight. A Reorder Buffer can easily be used to implement Branch Prediction, -because, just as with an Exception, the ROB needs to be cleared out +because, just as with an Exception, the ROB can to be cleared out (flushed) if the branch is mispredicted. As it is necessary to respect Exceptions, the logic has to exist to clear out the ROB: Branch Prediction simply uses this pre-existing logic. @@ -110,5 +110,7 @@ Whilst nothing's firmly set in stone, here, as we have a Charter that requires unanimous decision-making from contributors, so far it's leaning towards Reorder Buffers and Tomasulo as a good, clean fit. In part that is down to more research having been done on that particular algorithm. +For completeness, scoreboarding and explicit register renaming need +to be properly and comprehensively investigted. More as it happens...