add verilog-wishbone (for async bridge) to hdl-dev-ls2
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 11:51:02 +0000 (12:51 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 11:51:05 +0000 (12:51 +0100)
commitf88d6a87dbb070ce92b38b9061766f2b3fc29b84
tree70776560639f09e86874ae0c5e272be73b450228
parent79cda71f73537fcb51f78ea6d3083a66b1f9334b
add verilog-wishbone (for async bridge) to hdl-dev-ls2
hdl-dev-ls2