update comments

[ieee754fpu.git] / src / add / concurrentunit.py

diff --git a/src/add/concurrentunit.py b/src/add/concurrentunit.py
index 907cb68ab7f866281287791148f06458d92a43ad..c0053c8b5f26a3d6435d2987f114023621835950 100644 (file)
--- a/src/add/concurrentunit.py
+++ b/src/add/concurrentunit.py
@@ -6,7 +6,7 @@ from math import log
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage)
+from singlepipe import PassThroughStage
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe