rename BufPipe example to ExampleBufPipe

[ieee754fpu.git] / src / add / example_buf_pipe.py

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 8f3742259518750dd93f005276ac4bd1f19e672b..00eecc3ecd37db7b603c1dd4f50ce84e1b98ca52 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -70,7 +70,7 @@ class ExampleStage:
     def __init__(self):
         """ i_data can be a DIFFERENT type from everything else
             o_data, r_data and result are best of the same type.
-            however this is not strictly the case.  an intermediate
+            however this is not strictly necessary.  an intermediate
             transformation process could hypothetically be applied, however
             it is result and r_data that definitively need to be of the same
             (intermediary) type, as it is both result and r_data that
@@ -93,7 +93,9 @@ class ExampleStage:
         return self.result.eq(self.i_data + 1)
 
     def update_buffer(self):
-        """ copies the result into the intermediate register r_data
+        """ copies the result into the intermediate register r_data,
+            which will need to be outputted on a subsequent cycle
+            prior to allowing "normal" operation.
         """
         return self.r_data.eq(self.result)
 
@@ -113,23 +115,23 @@ class ExampleStage:
 class IOAckIn:
 
     def __init__(self):
-        self.p_valid = Signal()  # >>in - comes in from PREVIOUS stage
+        self.p_valid = Signal() # >>in - comes in from PREVIOUS stage
         self.n_ready = Signal() # in<< - comes in from the NEXT stage
 
 
 class IOAckOut:
 
     def __init__(self):
-        self.n_valid = Signal()  # out>> - goes out to the NEXT stage
+        self.n_valid = Signal() # out>> - goes out to the NEXT stage
         self.p_ready = Signal() # <<out - goes out to the PREVIOUS stage
 
 
 class BufferedPipeline:
     """ buffered pipeline stage
 
-        stage-1   i.p_valid  >>in   stage   o.n_valid  out>>   stage+1
+        stage-1   i.p_valid >>in   stage   o.n_valid out>>   stage+1
         stage-1   o.p_ready <<out  stage   i.n_ready <<in    stage+1
-        stage-1   i_data   >>in   stage   o_data   out>>   stage+1
+        stage-1   i_data    >>in   stage   o_data    out>>   stage+1
                               |             |
                               +------->  process
                               |             |
@@ -150,13 +152,9 @@ class BufferedPipeline:
         m = Module()
 
         # establish some combinatorial temporaries
-        o_p_readyn = Signal(reset_less=True)
         o_n_validn = Signal(reset_less=True)
-        i_n_readyn = Signal(reset_less=True)
         i_p_valid_o_p_ready = Signal(reset_less=True)
-        m.d.comb += [i_n_readyn.eq(~self.i.n_ready),
-                     o_n_validn.eq(~self.o.n_valid),
-                     o_p_readyn.eq(~self.o.p_ready),
+        m.d.comb += [o_n_validn.eq(~self.o.n_valid),
                      i_p_valid_o_p_ready.eq(self.i.p_valid & self.o.p_ready),
         ]
 
@@ -205,7 +203,7 @@ class BufferedPipeline:
                ]
 
 
-class BufPipe(BufferedPipeline):
+class ExampleBufPipe(BufferedPipeline):
 
     def __init__(self):
         BufferedPipeline.__init__(self)