add comment about ports needing flattening

[ieee754fpu.git] / src / add / example_buf_pipe.py

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index f760ce3948e0e96f3b7d18d18636f50d0f93c2c7..037d35db30070c4d0133ff1358f7bbd40863ee70 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -156,7 +156,7 @@ class PipelineBase:
     def ports(self):
         return [self.p.i_valid, self.n.i_ready,
                 self.n.o_valid, self.p.o_ready,
-                self.p.i_data, self.n.o_data
+                self.p.i_data, self.n.o_data   # XXX need flattening!
                ]
 
 
@@ -210,8 +210,8 @@ class BufferedPipeline(PipelineBase):
         ]
 
         # store result of processing in combinatorial temporary
-        with m.If(self.p.i_valid): # input is valid: process it
-            m.d.comb += eq(result, self.stage.process(self.p.i_data))
+        #with m.If(self.p.i_valid): # input is valid: process it
+        m.d.comb += eq(result, self.stage.process(self.p.i_data))
         # if not in stall condition, update the temporary register
         with m.If(self.p.o_ready): # not stalled
             m.d.sync += eq(r_data, result) # update buffer