from nmigen import Signal, Cat, Const, Mux, Module
from nmigen.cli import verilog, rtlil
+from nmigen.hdl.rec import Record, Layout
+
from collections.abc import Sequence
class PrevControl:
""" contains signals that come *from* the previous stage (both in and out)
- * i_valid: input from previous stage indicating incoming data is valid
+ * i_valid: previous stage indicating all incoming data is valid.
+ may be a multi-bit signal, where all bits are required
+ to be asserted to indicate "valid".
* o_ready: output to next stage indicating readiness to accept data
* i_data : an input - added by the user of this class
"""
- def __init__(self):
- self.i_valid = Signal(name="p_i_valid") # >>in
- self.o_ready = Signal(name="p_o_ready") # <<out
+ def __init__(self, i_width=1):
+ self.i_valid = Signal(i_width, name="p_i_valid") # prev >>in self
+ self.o_ready = Signal(name="p_o_ready") # prev <<out self
def connect_in(self, prev):
""" helper function to connect stage to an input source. do not
* o_data : an output - added by the user of this class
"""
def __init__(self):
- self.o_valid = Signal(name="n_o_valid") # out>>
- self.i_ready = Signal(name="n_i_ready") # <<in
+ self.o_valid = Signal(name="n_o_valid") # self out>> next
+ self.i_ready = Signal(name="n_i_ready") # self <<in next
def connect_to_next(self, nxt):
""" helper function to connect to the next stage data/valid/ready.
def eq(o, i):
+ """ makes signals equal: a helper routine which identifies if it is being
+ passsed a list (or tuple) of objects, and calls the objects' eq
+ function.
+
+ complex objects (classes) can be used: they must follow the
+ convention of having an eq member function, which takes the
+ responsibility of further calling eq and returning a list of
+ eq assignments
+
+ Record is a special (unusual, recursive) case, where the input
+ is specified as a dictionary (which may contain further dictionaries,
+ recursively), where the field names of the dictionary must match
+ the Record's field spec.
+ """
if not isinstance(o, Sequence):
o, i = [o], [i]
res = []
for (ao, ai) in zip(o, i):
- res.append(ao.eq(ai))
+ #print ("eq", ao, ai)
+ if isinstance(ao, Record):
+ for idx, (field_name, field_shape, _) in enumerate(ao.layout):
+ if isinstance(field_shape, Layout):
+ rres = eq(ao.fields[field_name], ai.fields[field_name])
+ else:
+ rres = eq(ao.fields[field_name], ai[field_name])
+ res += rres
+ else:
+ res.append(ao.eq(ai))
return res
class PipelineBase:
""" Common functions for Pipeline API
"""
- def __init__(self, stage):
+ def __init__(self, stage, in_multi=None):
""" pass in a "stage" which may be either a static class or a class
- instance, which has three functions:
+ instance, which has four functions (one optional):
* ispec: returns input signals according to the input specification
* ispec: returns output signals to the output specification
* process: takes an input instance and returns processed data
+ * setup: performs any module linkage if the stage uses one.
User must also:
* add i_data member to PrevControl and
self.stage = stage
# set up input and output IO ACK (prev/next ready/valid)
- self.p = PrevControl()
+ self.p = PrevControl(in_multi)
self.n = NextControl()
def connect_to_next(self, nxt):
def ports(self):
return [self.p.i_valid, self.n.i_ready,
self.n.o_valid, self.p.o_ready,
- self.p.i_data, self.n.o_data
+ self.p.i_data, self.n.o_data # XXX need flattening!
]
# set up the input and output data
self.p.i_data = stage.ispec() # input type
- self.r_data = stage.ospec() # all these are output type
- self.result = stage.ospec()
self.n.o_data = stage.ospec()
- def update_buffer(self):
- """ copies the result into the intermediate register r_data,
- which will need to be outputted on a subsequent cycle
- prior to allowing "normal" operation.
- """
- return eq(self.r_data, self.result)
-
- def update_output(self):
- """ copies the (combinatorial) result into the output
- """
- return eq(self.n.o_data, self.result)
-
- def flush_buffer(self):
- """ copies the *intermediate* register r_data into the output
- """
- return eq(self.n.o_data, self.r_data)
-
def elaborate(self, platform):
m = Module()
+
+ result = self.stage.ospec()
+ r_data = self.stage.ospec()
if hasattr(self.stage, "setup"):
self.stage.setup(m, self.p.i_data)
# establish some combinatorial temporaries
+ p_i_valid = Signal(reset_less=True)
o_n_validn = Signal(reset_less=True)
i_p_valid_o_p_ready = Signal(reset_less=True)
- m.d.comb += [o_n_validn.eq(~self.n.o_valid),
- i_p_valid_o_p_ready.eq(self.p.i_valid & self.p.o_ready),
+ vlen = len(self.p.i_valid)
+ if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
+ all1s = Const(-1, (len(self.p.i_valid), False))
+ m.d.comb += p_i_valid.eq(self.p.i_valid == all1s)
+ else: # single-bit i_valid case
+ m.d.comb += p_i_valid.eq(self.p.i_valid)
+ m.d.comb += [ o_n_validn.eq(~self.n.o_valid),
+ i_p_valid_o_p_ready.eq(p_i_valid & self.p.o_ready),
]
# store result of processing in combinatorial temporary
- with m.If(self.p.i_valid): # input is valid: process it
- m.d.comb += eq(self.result, self.stage.process(self.p.i_data))
+ #with m.If(self.p.i_valid): # input is valid: process it
+ m.d.comb += eq(result, self.stage.process(self.p.i_data))
# if not in stall condition, update the temporary register
with m.If(self.p.o_ready): # not stalled
- m.d.sync += self.update_buffer()
+ m.d.sync += eq(r_data, result) # update buffer
#with m.If(self.p.i_rst): # reset
# m.d.sync += self.n.o_valid.eq(0)
with m.If(self.n.i_ready): # next stage is ready
with m.If(self.p.o_ready): # not stalled
# nothing in buffer: send (processed) input direct to output
- m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
- self.update_output(),
+ m.d.sync += [self.n.o_valid.eq(p_i_valid),
+ eq(self.n.o_data, result), # update output
]
with m.Else(): # p.o_ready is false, and something is in buffer.
# Flush the [already processed] buffer to the output port.
m.d.sync += [self.n.o_valid.eq(1),
- self.flush_buffer(),
+ eq(self.n.o_data, r_data), # flush buffer
# clear stall condition, declare register empty.
self.p.o_ready.eq(1),
]
# (n.i_ready) is false here: next stage is ready
with m.Elif(o_n_validn): # next stage being told "ready"
- m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
+ m.d.sync += [self.n.o_valid.eq(p_i_valid),
self.p.o_ready.eq(1), # Keep the buffer empty
# set the output data (from comb result)
- self.update_output(),
+ eq(self.n.o_data, result),
]
# (n.i_ready) false and (n.o_valid) true:
with m.Elif(i_p_valid_o_p_ready):
# If next stage *is* ready, and not stalled yet, accept input
- m.d.sync += self.p.o_ready.eq(~(self.p.i_valid & self.n.o_valid))
+ m.d.sync += self.p.o_ready.eq(~(p_i_valid & self.n.o_valid))
return m
"""A simple pipeline stage containing combinational logic that can execute
completely in one clock cycle.
- Parameters:
- -----------
- input_shape : int or tuple or None
- the shape of ``input.data`` and ``comb_input``
- output_shape : int or tuple or None
- the shape of ``output.data`` and ``comb_output``
- name : str
- the name
-
Attributes:
-----------
input : StageInput
The pipeline input
output : StageOutput
The pipeline output
- comb_input : Signal, input_shape
- The input to the combinatorial logic
- comb_output: Signal, output_shape
+ r_data : Signal, input_shape
+ A temporary (buffered) copy of a prior (valid) input
+ result: Signal, output_shape
The output of the combinatorial logic
"""
# set up the input and output data
self.p.i_data = stage.ispec() # input type
- self.r_data = stage.ispec() # input type
- self.result = stage.ospec() # output data
self.n.o_data = stage.ospec() # output type
- self.n.o_data.name = "outdata"
def elaborate(self, platform):
m = Module()
+
+ r_data = self.stage.ispec() # input type
+ result = self.stage.ospec() # output data
if hasattr(self.stage, "setup"):
- self.stage.setup(m, self.r_data)
- m.d.comb += eq(self.result, self.stage.process(self.r_data))
+ self.stage.setup(m, r_data)
+
+ m.d.comb += eq(result, self.stage.process(r_data))
m.d.comb += self.n.o_valid.eq(self._data_valid)
m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
m.d.sync += self._data_valid.eq(self.p.i_valid | \
(~self.n.i_ready & self._data_valid))
with m.If(self.p.i_valid & self.p.o_ready):
- m.d.sync += eq(self.r_data, self.p.i_data)
- m.d.comb += eq(self.n.o_data, self.result)
+ m.d.sync += eq(r_data, self.p.i_data)
+ m.d.comb += eq(self.n.o_data, result)
return m
projects / ieee754fpu.git / blobdiff