class PrevControl:
""" contains signals that come *from* the previous stage (both in and out)
- * i_valid: input from previous stage indicating incoming data is valid
+ * i_valid: previous stage indicating all incoming data is valid.
+ may be a multi-bit signal, where all bits are required
+ to be asserted to indicate "valid".
* o_ready: output to next stage indicating readiness to accept data
* i_data : an input - added by the user of this class
"""
- def __init__(self):
- self.i_valid = Signal(name="p_i_valid") # prev >>in self
+ def __init__(self, i_width=1):
+ self.i_valid = Signal(i_width, name="p_i_valid") # prev >>in self
self.o_ready = Signal(name="p_o_ready") # prev <<out self
def connect_in(self, prev):
passsed a list (or tuple) of objects, and calls the objects' eq
function.
+ complex objects (classes) can be used: they must follow the
+ convention of having an eq member function, which takes the
+ responsibility of further calling eq and returning a list of
+ eq assignments
+
Record is a special (unusual, recursive) case, where the input
is specified as a dictionary (which may contain further dictionaries,
recursively), where the field names of the dictionary must match
class PipelineBase:
""" Common functions for Pipeline API
"""
- def __init__(self, stage):
+ def __init__(self, stage, in_multi=None):
""" pass in a "stage" which may be either a static class or a class
- instance, which has three functions:
+ instance, which has four functions (one optional):
* ispec: returns input signals according to the input specification
* ispec: returns output signals to the output specification
* process: takes an input instance and returns processed data
+ * setup: performs any module linkage if the stage uses one.
User must also:
* add i_data member to PrevControl and
self.stage = stage
# set up input and output IO ACK (prev/next ready/valid)
- self.p = PrevControl()
+ self.p = PrevControl(in_multi)
self.n = NextControl()
def connect_to_next(self, nxt):
self.stage.setup(m, self.p.i_data)
# establish some combinatorial temporaries
+ p_i_valid = Signal(reset_less=True)
o_n_validn = Signal(reset_less=True)
i_p_valid_o_p_ready = Signal(reset_less=True)
- m.d.comb += [o_n_validn.eq(~self.n.o_valid),
- i_p_valid_o_p_ready.eq(self.p.i_valid & self.p.o_ready),
+ vlen = len(self.p.i_valid)
+ if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
+ all1s = Const(-1, (len(self.p.i_valid), False))
+ m.d.comb += p_i_valid.eq(self.p.i_valid == all1s)
+ else: # single-bit i_valid case
+ m.d.comb += p_i_valid.eq(self.p.i_valid)
+ m.d.comb += [ o_n_validn.eq(~self.n.o_valid),
+ i_p_valid_o_p_ready.eq(p_i_valid & self.p.o_ready),
]
# store result of processing in combinatorial temporary
with m.If(self.n.i_ready): # next stage is ready
with m.If(self.p.o_ready): # not stalled
# nothing in buffer: send (processed) input direct to output
- m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
+ m.d.sync += [self.n.o_valid.eq(p_i_valid),
eq(self.n.o_data, result), # update output
]
with m.Else(): # p.o_ready is false, and something is in buffer.
# (n.i_ready) is false here: next stage is ready
with m.Elif(o_n_validn): # next stage being told "ready"
- m.d.sync += [self.n.o_valid.eq(self.p.i_valid),
+ m.d.sync += [self.n.o_valid.eq(p_i_valid),
self.p.o_ready.eq(1), # Keep the buffer empty
# set the output data (from comb result)
eq(self.n.o_data, result),
# (n.i_ready) false and (n.o_valid) true:
with m.Elif(i_p_valid_o_p_ready):
# If next stage *is* ready, and not stalled yet, accept input
- m.d.sync += self.p.o_ready.eq(~(self.p.i_valid & self.n.o_valid))
+ m.d.sync += self.p.o_ready.eq(~(p_i_valid & self.n.o_valid))
return m
"""A simple pipeline stage containing combinational logic that can execute
completely in one clock cycle.
- Parameters:
- -----------
- input_shape : int or tuple or None
- the shape of ``input.data`` and ``comb_input``
- output_shape : int or tuple or None
- the shape of ``output.data`` and ``comb_output``
- name : str
- the name
-
Attributes:
-----------
input : StageInput
The pipeline input
output : StageOutput
The pipeline output
- comb_input : Signal, input_shape
- The input to the combinatorial logic
- comb_output: Signal, output_shape
+ r_data : Signal, input_shape
+ A temporary (buffered) copy of a prior (valid) input
+ result: Signal, output_shape
The output of the combinatorial logic
"""
projects / ieee754fpu.git / blobdiff