update comments

[ieee754fpu.git] / src / add / fadd_state.py

diff --git a/src/add/fadd_state.py b/src/add/fadd_state.py
index 343f13ed21ab1b3ffa8e3d5dc42aa77a343aeebb..7ad88786027a4fdef707df6847e0c6447c455e30 100644 (file)
--- a/src/add/fadd_state.py
+++ b/src/add/fadd_state.py
@@ -7,6 +7,8 @@ from nmigen.cli import main, verilog
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
 
+from singlepipe import eq
+
 
 class FPADD(FPBase):
 
@@ -19,7 +21,7 @@ class FPADD(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPAdd
         """
         m = Module()
@@ -49,13 +51,15 @@ class FPADD(FPBase):
             # gets operand a
 
             with m.State("get_a"):
-                self.get_op(m, self.in_a, a, "get_b")
+                res = self.get_op(m, self.in_a, a, "get_b")
+                m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                self.get_op(m, self.in_b, b, "special_cases")
+                res = self.get_op(m, self.in_b, b, "special_cases")
+                m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases: NaNs, infs, zeros, denormalised