forgot to add submodules

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 20ada3ef18ca79da09fbbe15879e7b11849889a7..130d49e814d05028f5248206c4e87611e304a35b 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -28,6 +28,10 @@ class FPMUL(FPBase):
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
 
         with m.FSM() as fsm:
 
@@ -127,7 +131,8 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of, "corrections")
+                self.roundz(m, z, of.roundz)
+                m.next = "corrections"
 
             # ******
             # correction stage