update comments

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 16167514fb7fa7b2baf21ef1909c263c8eabbb82..a2ba41e75eb9bbf081d20158865171c21911940d 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         self.states.append(state)
         return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
@@ -41,8 +41,8 @@ class FPMUL(FPBase):
         m.submodules.b = b
         m.submodules.z = z
 
-        m.d.comb += a.v.eq(self.a.v)
-        m.d.comb += b.v.eq(self.b.v)
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
 
         with m.FSM() as fsm: