update comments

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 25944a83ef1ca136aa2868a609e847d8408171fe..a2ba41e75eb9bbf081d20158865171c21911940d 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -16,13 +16,13 @@ class FPMUL(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-       self.states = []
+        self.states = []
 
     def add_state(self, state):
-       self.states.append(state)
-       return state
+        self.states.append(state)
+        return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
@@ -41,8 +41,8 @@ class FPMUL(FPBase):
         m.submodules.b = b
         m.submodules.z = z
 
-        m.d.comb += a.v.eq(self.a.v)
-        m.d.comb += b.v.eq(self.b.v)
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
 
         with m.FSM() as fsm:
 
@@ -51,14 +51,14 @@ class FPMUL(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "get_b")
-               m.d.sync += eq([a, self.in_a.ack], res)
+                m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
                 res = self.get_op(m, self.in_b, b, "special_cases")
-               m.d.sync += eq([b, self.in_b.ack], res)
+                m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases