update comments

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8ddd45eb8bda5eb5a18dd14feeb56fab6124f876..a2ba41e75eb9bbf081d20158865171c21911940d 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,10 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpcommon.getop import FPGetOp
+from singlepipe import eq
+
 
 class FPMUL(FPBase):
 
@@ -14,7 +16,13 @@ class FPMUL(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-    def get_fragment(self, platform=None):
+        self.states = []
+
+    def add_state(self, state):
+        self.states.append(state)
+        return state
+
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
@@ -28,6 +36,13 @@ class FPMUL(FPBase):
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
+
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
 
         with m.FSM() as fsm:
 
@@ -35,13 +50,15 @@ class FPMUL(FPBase):
             # gets operand a
 
             with m.State("get_a"):
-                self.get_op(m, self.in_a, a, "get_b")
+                res = self.get_op(m, self.in_a, a, "get_b")
+                m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                self.get_op(m, self.in_b, b, "special_cases")
+                res = self.get_op(m, self.in_b, b, "special_cases")
+                m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases
@@ -127,7 +144,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of)
+                self.roundz(m, z, of.roundz)
                 m.next = "corrections"
 
             # ******