update comments

[ieee754fpu.git] / src / add / fpadd / add0.py

diff --git a/src/add/fpadd/add0.py b/src/add/fpadd/add0.py
index 7d84b74cfde77d347f962884c97803245f225c4e..76790fe22bbd4d48220e98b78d694b8ef2567180 100644 (file)
--- a/src/add/fpadd/add0.py
+++ b/src/add/fpadd/add0.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat 
+from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumBase
@@ -24,7 +24,7 @@ class FPAddStage0Data:
                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 
 
-class FPAddStage0Mod:
+class FPAddStage0Mod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width