update comments

[ieee754fpu.git] / src / add / fpadd / add0.py

diff --git a/src/add/fpadd/add0.py b/src/add/fpadd/add0.py
index cdeca5a0e370a0236891d36987c1eef4d3c72044..76790fe22bbd4d48220e98b78d694b8ef2567180 100644 (file)
--- a/src/add/fpadd/add0.py
+++ b/src/add/fpadd/add0.py
@@ -2,19 +2,11 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
-from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from fpbase import FPState, FPID
+from fpbase import FPNumBase
+from fpbase import FPState
 from fpcommon.denorm import FPSCData
 
 
@@ -32,7 +24,7 @@ class FPAddStage0Data:
                 self.tot.eq(i.tot), self.mid.eq(i.mid)]
 
 
-class FPAddStage0Mod:
+class FPAddStage0Mod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width