update comments

[ieee754fpu.git] / src / add / fpadd / add1.py

diff --git a/src/add/fpadd/add1.py b/src/add/fpadd/add1.py
index 08c27b8e0e3f0c8e3b080271f7ce90ace4aafe2e..679f5176d2d9227c41637d9fb9db2d6c08c6845d 100644 (file)
--- a/src/add/fpadd/add1.py
+++ b/src/add/fpadd/add1.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -11,7 +11,7 @@ from fpcommon.postcalc import FPAddStage1Data
 from fpadd.add0 import FPAddStage0Data
 
 
-class FPAddStage1Mod(FPState):
+class FPAddStage1Mod(FPState, Elaboratable):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """