update comments

[ieee754fpu.git] / src / add / fpadd / addstages.py

diff --git a/src/add/fpadd/addstages.py b/src/add/fpadd/addstages.py
index 39888148c0844f2e0d94611da746f9dbb550a1ce..f5703aeceaacd6c99855b9977aab4d95a8432b62 100644 (file)
--- a/src/add/fpadd/addstages.py
+++ b/src/add/fpadd/addstages.py
@@ -2,33 +2,27 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module
 from nmigen.cli import main, verilog
-from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
+from singlepipe import (StageChain, SimpleHandshake,
                         PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
 
-from fpbase import FPState, FPID
+from fpbase import FPState
 from fpcommon.denorm import FPSCData
 from fpcommon.postcalc import FPAddStage1Data
 from fpadd.align import FPAddAlignSingleMod
-from fpadd.add0 import (FPAddStage0Data, FPAddStage0Mod, FPAddStage0)
-from fpadd.add1 import (FPAddStage1Mod, FPAddStage1)
+from fpadd.add0 import FPAddStage0Mod
+from fpadd.add1 import FPAddStage1Mod
 
 
-class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
+class FPAddAlignSingleAdd(FPState, SimpleHandshake):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
         self.a1o = self.ospec()
 
     def ispec(self):