update comments

[ieee754fpu.git] / src / add / fpadd / pipeline.py

diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py
index 45b943eaa12641a496e8787b4ee16d7df5b43b8c..e244ee60e2f373d917de6eaeaca4a6e7f74d9f32 100644 (file)
--- a/src/add/fpadd/pipeline.py
+++ b/src/add/fpadd/pipeline.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage)
+from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 
@@ -29,7 +29,7 @@ class FPADDBasePipe(ControlBase):
         self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
-        m = Module()
+        m = ControlBase.elaborate(self, platform)
         m.submodules.scnorm = self.pipe1
         m.submodules.addalign = self.pipe2
         m.submodules.normpack = self.pipe3