update comments

[ieee754fpu.git] / src / add / fpadd / specialcases.py

diff --git a/src/add/fpadd/specialcases.py b/src/add/fpadd/specialcases.py
index d1c1b1fc6e8a5c05444909815323d348044c975a..6f9d1a08575773c3e57139c480a1b8b84ed5b677 100644 (file)
--- a/src/add/fpadd/specialcases.py
+++ b/src/add/fpadd/specialcases.py
@@ -6,8 +6,8 @@ from nmigen import Module, Signal, Cat, Const
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn
-from singlepipe import UnbufferedPipeline, StageChain
+from fpbase import FPNumDecode
+from singlepipe import SimpleHandshake, StageChain
 
 from fpbase import FPState, FPID
 from fpcommon.getop import FPADDBaseData
@@ -47,12 +47,14 @@ class FPAddSpecialCasesMod:
         m.submodules.sc_out_z = self.o.z
 
         # decode: XXX really should move to separate stage
-        a1 = FPNumIn(None, self.width)
-        b1 = FPNumIn(None, self.width)
+        a1 = FPNumDecode(None, self.width)
+        b1 = FPNumDecode(None, self.width)
         m.submodules.sc_decode_a = a1
         m.submodules.sc_decode_b = b1
-        m.d.comb += [a1.decode(self.i.a),
-                     b1.decode(self.i.b),
+        m.d.comb += [a1.v.eq(self.i.a),
+                     b1.v.eq(self.i.b),
+                     self.o.a.eq(a1),
+                     self.o.b.eq(b1)
                     ]
 
         s_nomatch = Signal(reset_less=True)
@@ -62,10 +64,22 @@ class FPAddSpecialCasesMod:
         m.d.comb += m_match.eq(a1.m == b1.m)
 
         e_match = Signal(reset_less=True)
-        m.d.comb += m_match.eq(a1.e == b1.e)
+        m.d.comb += e_match.eq(a1.e == b1.e)
+
+        aeqmb = Signal(reset_less=True)
+        m.d.comb += aeqmb.eq(s_nomatch & m_match & e_match)
+
+        abz = Signal(reset_less=True)
+        m.d.comb += abz.eq(a1.is_zero & b1.is_zero)
+
+        abnan = Signal(reset_less=True)
+        m.d.comb += abnan.eq(a1.is_nan | b1.is_nan)
+
+        bexp128s = Signal(reset_less=True)
+        m.d.comb += bexp128s.eq(b1.exp_128 & s_nomatch)
 
         # if a is NaN or b is NaN return NaN
-        with m.If(a1.is_nan | b1.is_nan):
+        with m.If(abnan):
             m.d.comb += self.o.out_do_z.eq(1)
             m.d.comb += self.o.z.nan(0)
 
@@ -97,7 +111,7 @@ class FPAddSpecialCasesMod:
             m.d.comb += self.o.out_do_z.eq(1)
             m.d.comb += self.o.z.inf(a1.s)
             # if a is inf and signs don't match return NaN
-            with m.If(b1.exp_128 & s_nomatch):
+            with m.If(bexp128s):
                 m.d.comb += self.o.z.nan(0)
 
         # if b is inf return inf
@@ -106,7 +120,7 @@ class FPAddSpecialCasesMod:
             m.d.comb += self.o.z.inf(b1.s)
 
         # if a is zero and b zero return signed-a/b
-        with m.Elif(a1.is_zero & b1.is_zero):
+        with m.Elif(abz):
             m.d.comb += self.o.out_do_z.eq(1)
             m.d.comb += self.o.z.create(a1.s & b1.s, b1.e, b1.m[3:-1])
 
@@ -121,15 +135,13 @@ class FPAddSpecialCasesMod:
             m.d.comb += self.o.z.create(a1.s, a1.e, a1.m[3:-1])
 
         # if a equal to -b return zero (+ve zero)
-        with m.Elif(s_nomatch & m_match & e_match):
+        with m.Elif(aeqmb):
             m.d.comb += self.o.out_do_z.eq(1)
             m.d.comb += self.o.z.zero(0)
 
         # Denormalised Number checks next, so pass a/b data through
         with m.Else():
             m.d.comb += self.o.out_do_z.eq(0)
-            m.d.comb += self.o.a.eq(a1)
-            m.d.comb += self.o.b.eq(b1)
 
         m.d.comb += self.o.oz.eq(self.o.z.v)
         m.d.comb += self.o.mid.eq(self.i.mid)
@@ -164,7 +176,7 @@ class FPAddSpecialCases(FPState):
             m.next = "denormalise"
 
 
-class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
+class FPAddSpecialCasesDeNorm(FPState, SimpleHandshake):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -174,7 +186,7 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
         FPState.__init__(self, "special_cases")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self) # pipe is its own stage
+        SimpleHandshake.__init__(self, self) # pipe is its own stage
         self.out = self.ospec()
 
     def ispec(self):