from nmigen.cli import main, verilog
from math import log
-from fpbase import FPOp
+from fpbase import FPOpIn, FPOpOut
from fpbase import Trigger
-from singlepipe import (StageChain, UnbufferedPipeline)
+from singlepipe import (StageChain, SimpleHandshake)
from fpbase import FPState, FPID
from fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op)
class FPOpData:
def __init__(self, width, id_wid):
- self.z = FPOp(width)
+ self.z = FPOpOut(width)
+ self.z.data_o = Signal(width)
self.mid = Signal(id_wid, reset_less=True)
+ def __iter__(self):
+ yield self.z
+ yield self.mid
+
def eq(self, i):
return [self.z.eq(i.z), self.mid.eq(i.mid)]
def ports(self):
- return [self.z, self.mid]
+ return list(self)
class FPADDBaseMod:
self.states.append(state)
return state
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
self.in_t.ack.eq(self.mod.in_t.ack),
self.o.mid.eq(self.mod.o.mid),
self.o.z.v.eq(self.mod.o.z.v),
- self.o.z.stb.eq(self.mod.o.z.stb),
- self.mod.o.z.ack.eq(self.o.z.ack),
+ self.o.z.valid_o.eq(self.mod.o.z.valid_o),
+ self.mod.o.z.ready_i.eq(self.o.z.ready_i_test),
]
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
- m.d.sync += self.o.z.ack.eq(0) # likewise
+ m.d.sync += self.o.z.ready_i.eq(0) # likewise
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
- self.o.z.ack.eq(1),
+ self.o.z.ready_i.eq(1),
]
with m.Else():
# done: acknowledge, and write out id and value
rs = []
for i in range(rs_sz):
- in_a = FPOp(width)
- in_b = FPOp(width)
+ in_a = FPOpIn(width)
+ in_b = FPOpIn(width)
+ in_a.data_i = Signal(width)
+ in_b.data_i = Signal(width)
in_a.name = "in_a_%d" % i
in_b.name = "in_b_%d" % i
rs.append((in_a, in_b))
res = []
for i in range(rs_sz):
- out_z = FPOp(width)
+ out_z = FPOpOut(width)
+ out_z.data_o = Signal(width)
out_z.name = "out_z_%d" % i
res.append(out_z)
self.res = Array(res)
self.states.append(state)
return state
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
- m.submodules += self.rs
+ #m.submodules += self.rs
in_a = self.rs[0][0]
in_b = self.rs[0][1]