update comments

[ieee754fpu.git] / src / add / fpcommon / denorm.py

diff --git a/src/add/fpcommon/denorm.py b/src/add/fpcommon/denorm.py
index 32e775404f0c4490c2295c6cc311547b9c4ffeaa..9fbbc9765d00520a93ffa6ce83f0cbf5bfbc6b75 100644 (file)
--- a/src/add/fpcommon/denorm.py
+++ b/src/add/fpcommon/denorm.py
@@ -2,20 +2,12 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
+from fpbase import FPNumIn, FPNumOut, FPNumBase
 from fpbase import FPState
-from fpcommon.getop import (FPGetOpMod, FPGetOp, FPNumBase2Ops, FPADDBaseData,                              FPGet2OpMod, FPGet2Op)
 
 
 class FPSCData:
@@ -28,6 +20,14 @@ class FPSCData:
         self.out_do_z = Signal(reset_less=True)
         self.mid = Signal(id_wid, reset_less=True)
 
+    def __iter__(self):
+        yield from self.a
+        yield from self.b
+        yield from self.z
+        yield self.oz
+        yield self.out_do_z
+        yield self.mid
+
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]