# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
from nmigen.lib.coding import PriorityEncoder
from nmigen.cli import main, verilog
from math import log
from multipipe import PriorityCombMuxInPipe
from fpbase import FPState
+import nmoperator
-class FPGetOpMod:
+class FPGetOpMod(Elaboratable):
def __init__(self, width):
self.in_op = FPOpIn(width)
+ self.in_op.data_i = Signal(width)
self.out_op = Signal(width)
self.out_decode = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_decode.eq((self.in_op.o_ready) & \
- (self.in_op.i_valid_test))
+ m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
+ (self.in_op.valid_i_test))
m.submodules.get_op_in = self.in_op
#m.submodules.get_op_out = self.out_op
with m.If(self.out_decode):
""" links module to inputs and outputs
"""
setattr(m.submodules, self.state_from, self.mod)
- m.d.comb += self.mod.in_op.eq(in_op)
+ m.d.comb += nmoperator.eq(self.mod.in_op, in_op)
m.d.comb += self.out_decode.eq(self.mod.out_decode)
def action(self, m):
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += [
- self.in_op.o_ready.eq(0),
+ self.in_op.ready_o.eq(0),
self.out_op.eq(self.mod.out_op)
]
with m.Else():
- m.d.sync += self.in_op.o_ready.eq(1)
+ m.d.sync += self.in_op.ready_o.eq(1)
class FPNumBase2Ops:
PrevControl.__init__(self)
self.width = width
self.id_wid = id_wid
- self.i_data = self.ispec()
- self.i = self.i_data
+ self.data_i = self.ispec()
+ self.i = self.data_i
self.o = self.ospec()
def ispec(self):
m = PrevControl.elaborate(self, platform)
with m.If(self.trigger):
m.d.comb += [
- self.o.eq(self.i_data),
+ self.o.eq(self.data_i),
]
return m
def trigger_setup(self, m, in_stb, in_ack):
""" links stb/ack
"""
- m.d.comb += self.mod.i_valid.eq(in_stb)
- m.d.comb += in_ack.eq(self.mod.o_ready)
+ m.d.comb += self.mod.valid_i.eq(in_stb)
+ m.d.comb += in_ack.eq(self.mod.ready_o)
def setup(self, m, i):
""" links module to inputs and outputs
"""
m.submodules.get_ops = self.mod
m.d.comb += self.mod.i.eq(i)
- m.d.comb += self.out_ack.eq(self.mod.o_ready)
+ m.d.comb += self.out_ack.eq(self.mod.ready_o)
m.d.comb += self.out_decode.eq(self.mod.trigger)
def process(self, i):
with m.If(self.out_decode):
m.next = self.out_state
m.d.sync += [
- self.mod.o_ready.eq(0),
+ self.mod.ready_o.eq(0),
self.o.eq(self.mod.o),
]
with m.Else():
- m.d.sync += self.mod.o_ready.eq(1)
+ m.d.sync += self.mod.ready_o.eq(1)