update comments

[ieee754fpu.git] / src / add / fpcommon / getop.py

diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py
index 607384318b1e136ae7fb586f78c5655232c0cc5b..1988997a8948abc7bad5b0c1276736c0e2fd3dc8 100644 (file)
--- a/src/add/fpcommon/getop.py
+++ b/src/add/fpcommon/getop.py
@@ -2,30 +2,33 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
+from fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
+from singlepipe import (ControlBase, StageChain, SimpleHandshake,
+                        PassThroughStage, PrevControl)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 
 from fpbase import FPState
+import nmoperator
 
 
-class FPGetOpMod:
+class FPGetOpMod(Elaboratable):
     def __init__(self, width):
-        self.in_op = FPOp(width)
+        self.in_op = FPOpIn(width)
+        self.in_op.data_i = Signal(width)
         self.out_op = Signal(width)
         self.out_decode = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
+        m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
+                                       (self.in_op.valid_i_test))
         m.submodules.get_op_in = self.in_op
         #m.submodules.get_op_out = self.out_op
         with m.If(self.out_decode):
@@ -51,18 +54,18 @@ class FPGetOp(FPState):
         """ links module to inputs and outputs
         """
         setattr(m.submodules, self.state_from, self.mod)
-        m.d.comb += self.mod.in_op.eq(in_op)
+        m.d.comb += nmoperator.eq(self.mod.in_op, in_op)
         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 
     def action(self, m):
         with m.If(self.out_decode):
             m.next = self.out_state
             m.d.sync += [
-                self.in_op.ack.eq(0),
+                self.in_op.ready_o.eq(0),
                 self.out_op.eq(self.mod.out_op)
             ]
         with m.Else():
-            m.d.sync += self.in_op.ack.eq(1)
+            m.d.sync += self.in_op.ready_o.eq(1)
 
 
 class FPNumBase2Ops:
@@ -95,12 +98,13 @@ class FPADDBaseData:
         return [self.a, self.b, self.mid]
 
 
-class FPGet2OpMod(Trigger):
+class FPGet2OpMod(PrevControl):
     def __init__(self, width, id_wid):
-        Trigger.__init__(self)
+        PrevControl.__init__(self)
         self.width = width
         self.id_wid = id_wid
-        self.i = self.ispec()
+        self.data_i = self.ispec()
+        self.i = self.data_i
         self.o = self.ospec()
 
     def ispec(self):
@@ -113,10 +117,10 @@ class FPGet2OpMod(Trigger):
         return self.o
 
     def elaborate(self, platform):
-        m = Trigger.elaborate(self, platform)
+        m = PrevControl.elaborate(self, platform)
         with m.If(self.trigger):
             m.d.comb += [
-                self.o.eq(self.i),
+                self.o.eq(self.data_i),
             ]
         return m
 
@@ -143,15 +147,15 @@ class FPGet2Op(FPState):
     def trigger_setup(self, m, in_stb, in_ack):
         """ links stb/ack
         """
-        m.d.comb += self.mod.stb.eq(in_stb)
-        m.d.comb += in_ack.eq(self.mod.ack)
+        m.d.comb += self.mod.valid_i.eq(in_stb)
+        m.d.comb += in_ack.eq(self.mod.ready_o)
 
     def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.get_ops = self.mod
         m.d.comb += self.mod.i.eq(i)
-        m.d.comb += self.out_ack.eq(self.mod.ack)
+        m.d.comb += self.out_ack.eq(self.mod.ready_o)
         m.d.comb += self.out_decode.eq(self.mod.trigger)
 
     def process(self, i):
@@ -161,10 +165,10 @@ class FPGet2Op(FPState):
         with m.If(self.out_decode):
             m.next = self.out_state
             m.d.sync += [
-                self.mod.ack.eq(0),
+                self.mod.ready_o.eq(0),
                 self.o.eq(self.mod.o),
             ]
         with m.Else():
-            m.d.sync += self.mod.ack.eq(1)
+            m.d.sync += self.mod.ready_o.eq(1)