update comments

[ieee754fpu.git] / src / add / fpcommon / pack.py

diff --git a/src/add/fpcommon/pack.py b/src/add/fpcommon/pack.py
index c12c70c0b0045d8d4d80e9a80320a5e23297b7f7..1464883cdeec57ed4fcc002ecb192b557f7db4fc 100644 (file)
--- a/src/add/fpcommon/pack.py
+++ b/src/add/fpcommon/pack.py
@@ -2,36 +2,24 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
-from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from fpbase import FPState, FPID
+from fpbase import FPNumOut
+from fpbase import FPState
 from fpcommon.roundz import FPRoundData
+from singlepipe import Object
 
 
-class FPPackData:
+class FPPackData(Object):
 
     def __init__(self, width, id_wid):
+        Object.__init__(self)
         self.z = Signal(width, reset_less=True)
         self.mid = Signal(id_wid, reset_less=True)
 
-    def eq(self, i):
-        return [self.z.eq(i.z), self.mid.eq(i.mid)]
-
-    def ports(self):
-        return [self.z, self.mid]
-
 
-class FPPackMod:
+class FPPackMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width