update comments

[ieee754fpu.git] / src / add / fpcommon / postcalc.py

diff --git a/src/add/fpcommon/postcalc.py b/src/add/fpcommon/postcalc.py
index 8fbac39274d273a8e142a947bd2fe0b621d1b11a..7111dc8a94f343f83052a86001d0a28b29555ef2 100644 (file)
--- a/src/add/fpcommon/postcalc.py
+++ b/src/add/fpcommon/postcalc.py
@@ -2,17 +2,8 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
-from nmigen.cli import main, verilog
-from math import log
-
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
+from nmigen import Signal
+from fpbase import Overflow, FPNumBase
 
 class FPAddStage1Data:
 
@@ -23,6 +14,13 @@ class FPAddStage1Data:
         self.of = Overflow()
         self.mid = Signal(id_wid, reset_less=True)
 
+    def __iter__(self):
+        yield from self.z
+        yield self.out_do_z
+        yield self.oz
+        yield from self.of
+        yield self.mid
+
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
                 self.of.eq(i.of), self.mid.eq(i.mid)]