update comments

[ieee754fpu.git] / src / add / fpcommon / postnormalise.py

diff --git a/src/add/fpcommon/postnormalise.py b/src/add/fpcommon/postnormalise.py
index 18a7b77c31e8691e8d474187e05f29875a8e6c30..b072490f0374fab9872c9c846fa9efa161480c07 100644 (file)
--- a/src/add/fpcommon/postnormalise.py
+++ b/src/add/fpcommon/postnormalise.py
@@ -2,18 +2,13 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Elaboratable
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
+from fpbase import Overflow, FPNumBase
+from fpbase import MultiShiftRMerge
 from fpbase import FPState
 from .postcalc import FPAddStage1Data
 
@@ -32,7 +27,7 @@ class FPNorm1Data:
                 self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
 
 
-class FPNorm1ModSingle:
+class FPNorm1ModSingle(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width