update comments

[ieee754fpu.git] / src / add / fpcommon / roundz.py

diff --git a/src/add/fpcommon/roundz.py b/src/add/fpcommon/roundz.py
index 24c49b87d9c67059bd634932cf61306310a0eab4..420d6669a10799190f23585b1d09c31dad118af2 100644 (file)
--- a/src/add/fpcommon/roundz.py
+++ b/src/add/fpcommon/roundz.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
 from fpbase import FPNumBase
@@ -23,7 +23,7 @@ class FPRoundData:
                 self.mid.eq(i.mid)]
 
 
-class FPRoundMod:
+class FPRoundMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width