update comments

[ieee754fpu.git] / src / add / multipipe.py

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 3235359dc84a917785d559755f769362649862de..e24703f8fcbea1125c00c1a335ca2bb1290c32aa 100644 (file)
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -15,6 +15,7 @@ from nmigen import Signal, Cat, Const, Mux, Module, Array, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.hdl.rec import Record, Layout
+from stageapi import _spec
 
 from collections.abc import Sequence
 
@@ -162,9 +163,15 @@ class CombMultiOutPipeline(MultiOutControlBase):
         self.n_mux = n_mux
 
         # set up the input and output data
-        self.p.data_i = stage.ispec() # input type
+        self.p.data_i = _spec(stage.ispec, 'data_i') # input type
         for i in range(n_len):
-            self.n[i].data_o = stage.ospec() # output type
+            name = 'data_o_%d' % i
+            self.n[i].data_o = _spec(stage.ospec, name) # output type
+
+    def process(self, i):
+        if hasattr(self.stage, "process"):
+            return self.stage.process(i)
+        return i
 
     def elaborate(self, platform):
         m = MultiOutControlBase.elaborate(self, platform)
@@ -173,7 +180,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
             m.submodules += self.n_mux
 
         # need buffer register conforming to *input* spec
-        r_data = self.stage.ispec() # input type
+        r_data = _spec(self.stage.ispec, 'r_data') # input type
         if hasattr(self.stage, "setup"):
             self.stage.setup(m, r_data)
 
@@ -196,7 +203,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
                                     (~self.n[mid].ready_i & data_valid))
         with m.If(pv):
             m.d.comb += eq(r_data, self.p.data_i)
-        m.d.comb += eq(self.n[mid].data_o, self.stage.process(r_data))
+        m.d.comb += eq(self.n[mid].data_o, self.process(r_data))
 
         return m
 
@@ -223,8 +230,14 @@ class CombMultiInPipeline(MultiInControlBase):
 
         # set up the input and output data
         for i in range(p_len):
-            self.p[i].data_i = stage.ispec() # input type
-        self.n.data_o = stage.ospec()
+            name = 'data_i_%d' % i
+            self.p[i].data_i = _spec(stage.ispec, name) # input type
+        self.n.data_o = _spec(stage.ospec, 'data_o')
+
+    def process(self, i):
+        if hasattr(self.stage, "process"):
+            return self.stage.process(i)
+        return i
 
     def elaborate(self, platform):
         m = MultiInControlBase.elaborate(self, platform)
@@ -238,7 +251,8 @@ class CombMultiInPipeline(MultiInControlBase):
         n_ready_in = []
         p_len = len(self.p)
         for i in range(p_len):
-            r = self.stage.ispec() # input type
+            name = 'r_%d' % i
+            r = _spec(self.stage.ispec, name) # input type
             r_data.append(r)
             data_valid.append(Signal(name="data_valid", reset_less=True))
             p_valid_i.append(Signal(name="p_valid_i", reset_less=True))
@@ -277,7 +291,7 @@ class CombMultiInPipeline(MultiInControlBase):
             with m.If(vr):
                 m.d.comb += eq(r_data[i], self.p[i].data_i)
 
-        m.d.comb += eq(self.n.data_o, self.stage.process(r_data[mid]))
+        m.d.comb += eq(self.n.data_o, self.process(r_data[mid]))
 
         return m