with m.Else():
m.d.sync += self.mod.ack.eq(1)
+class FPNumBase2Ops:
+
+ def __init__(self, width, m_extra=True):
+ self.a = FPNumBase(width, m_extra)
+ self.b = FPNumBase(width, m_extra)
+
+ def eq(self, i):
+ return [self.a.eq(i.a), self.a.eq(i.b)]
+
class FPAddSpecialCasesMod:
""" special cases: NaNs, infs, zeros, denormalised
"""
def __init__(self, width):
- self.in_a = FPNumBase(width)
- self.in_b = FPNumBase(width)
- self.out_z = FPNumOut(width, False)
+ self.width = width
+ self.i = self.ispec()
+ self.out_z = self.ospec()
self.out_do_z = Signal(reset_less=True)
+ def ispec(self):
+ return FPNumBase2Ops(self.width)
+
+ def ospec(self):
+ return FPNumOut(self.width, False)
+
def setup(self, m, in_a, in_b, out_do_z):
""" links module to inputs and outputs
"""
m.submodules.specialcases = self
- m.d.comb += self.in_a.eq(in_a)
- m.d.comb += self.in_b.eq(in_b)
+ m.d.comb += self.i.a.eq(in_a)
+ m.d.comb += self.i.b.eq(in_b)
m.d.comb += out_do_z.eq(self.out_do_z)
def elaborate(self, platform):
m = Module()
- m.submodules.sc_in_a = self.in_a
- m.submodules.sc_in_b = self.in_b
+ m.submodules.sc_in_a = self.i.a
+ m.submodules.sc_in_b = self.i.b
m.submodules.sc_out_z = self.out_z
s_nomatch = Signal()
- m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
+ m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
m_match = Signal()
- m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
+ m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
# if a is NaN or b is NaN return NaN
- with m.If(self.in_a.is_nan | self.in_b.is_nan):
+ with m.If(self.i.a.is_nan | self.i.b.is_nan):
m.d.comb += self.out_do_z.eq(1)
m.d.comb += self.out_z.nan(0)
# m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
# if a is inf return inf (or NaN)
- with m.Elif(self.in_a.is_inf):
+ with m.Elif(self.i.a.is_inf):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.inf(self.in_a.s)
+ m.d.comb += self.out_z.inf(self.i.a.s)
# if a is inf and signs don't match return NaN
- with m.If(self.in_b.exp_128 & s_nomatch):
+ with m.If(self.i.b.exp_128 & s_nomatch):
m.d.comb += self.out_z.nan(0)
# if b is inf return inf
- with m.Elif(self.in_b.is_inf):
+ with m.Elif(self.i.b.is_inf):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.inf(self.in_b.s)
+ m.d.comb += self.out_z.inf(self.i.b.s)
# if a is zero and b zero return signed-a/b
- with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
+ with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
- self.in_b.e,
- self.in_b.m[3:-1])
+ m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
+ self.i.b.e,
+ self.i.b.m[3:-1])
# if a is zero return b
- with m.Elif(self.in_a.is_zero):
+ with m.Elif(self.i.a.is_zero):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
- self.in_b.m[3:-1])
+ m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
+ self.i.b.m[3:-1])
# if b is zero return a
- with m.Elif(self.in_b.is_zero):
+ with m.Elif(self.i.b.is_zero):
m.d.comb += self.out_do_z.eq(1)
- m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
- self.in_a.m[3:-1])
+ m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
+ self.i.a.m[3:-1])
# if a equal to -b return zero (+ve zero)
- with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
+ with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
m.d.comb += self.out_do_z.eq(1)
m.d.comb += self.out_z.zero(0)
FPState.__init__(self, "special_cases")
FPID.__init__(self, id_wid)
self.mod = FPAddSpecialCasesMod(width)
- self.out_z = FPNumOut(width, False)
+ self.out_z = self.mod.ospec()
self.out_do_z = Signal(reset_less=True)
def setup(self, m, in_a, in_b, in_mid):
FPState.__init__(self, "special_cases")
FPID.__init__(self, id_wid)
self.smod = FPAddSpecialCasesMod(width)
- self.out_z = FPNumOut(width, False)
+ self.out_z = self.smod.ospec()
self.out_do_z = Signal(reset_less=True)
self.dmod = FPAddDeNormMod(width)
m.next = "put_z"
with m.Else():
m.next = "align"
- m.d.sync += self.out_a.eq(self.dmod.out_a)
- m.d.sync += self.out_b.eq(self.dmod.out_b)
+ m.d.sync += self.out_a.eq(self.dmod.o.a)
+ m.d.sync += self.out_b.eq(self.dmod.o.b)
class FPAddDeNormMod(FPState):
def __init__(self, width):
- self.in_a = FPNumBase(width)
- self.in_b = FPNumBase(width)
- self.out_a = FPNumBase(width)
- self.out_b = FPNumBase(width)
+ self.width = width
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return FPNumBase2Ops(self.width)
+
+ def ospec(self):
+ return FPNumBase2Ops(self.width)
def setup(self, m, in_a, in_b):
""" links module to inputs and outputs
"""
m.submodules.denormalise = self
- m.d.comb += self.in_a.eq(in_a)
- m.d.comb += self.in_b.eq(in_b)
+ m.d.comb += self.i.a.eq(in_a)
+ m.d.comb += self.i.b.eq(in_b)
def elaborate(self, platform):
m = Module()
- m.submodules.denorm_in_a = self.in_a
- m.submodules.denorm_in_b = self.in_b
- m.submodules.denorm_out_a = self.out_a
- m.submodules.denorm_out_b = self.out_b
+ m.submodules.denorm_in_a = self.i.a
+ m.submodules.denorm_in_b = self.i.b
+ m.submodules.denorm_out_a = self.o.a
+ m.submodules.denorm_out_b = self.o.b
# hmmm, don't like repeating identical code
- m.d.comb += self.out_a.eq(self.in_a)
- with m.If(self.in_a.exp_n127):
- m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
+ m.d.comb += self.o.a.eq(self.i.a)
+ with m.If(self.i.a.exp_n127):
+ m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
with m.Else():
- m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
+ m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
- m.d.comb += self.out_b.eq(self.in_b)
- with m.If(self.in_b.exp_n127):
- m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
+ m.d.comb += self.o.b.eq(self.i.b)
+ with m.If(self.i.b.exp_n127):
+ m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
with m.Else():
- m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
+ m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
return m
projects / ieee754fpu.git / blobdiff