def ospec(self):
return FPNumBase(self.width, False)
- def setup(self, m, in_z, out_z, modname):
+ def setup(self, m, in_z, out_z):
""" links module to inputs and outputs
"""
m.submodules.normalise = self
return m
+class FPNorm1Data:
+
+ def __init__(self, width):
+
+ self.roundz = Signal(reset_less=True)
+ self.z = FPNumBase(width, False)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.roundz.eq(i.roundz)]
+
class FPNorm1ModSingle:
def __init__(self, width):
self.width = width
self.i = self.ispec()
- self.o = self.ispec()
+ self.o = self.ospec()
def ispec(self):
return FPAddStage1Data(self.width)
def ospec(self):
- return FPAddStage1Data(self.width)
+ return FPNorm1Data(self.width)
def setup(self, m, in_z, in_of, out_z):
""" links module to inputs and outputs
pe = PriorityEncoder(mwid)
m.submodules.norm_pe = pe
+ of = Overflow()
+ m.d.comb += self.o.roundz.eq(of.roundz)
+
m.submodules.norm1_out_z = self.o.z
- m.submodules.norm1_out_overflow = self.o.of
+ m.submodules.norm1_out_overflow = of
m.submodules.norm1_in_z = self.i.z
m.submodules.norm1_in_overflow = self.i.of
m.d.comb += i.eq(self.i)
# initialise out from in (overridden below)
- m.d.comb += self.o.eq(i)
+ m.d.comb += self.o.z.eq(i.z)
+ m.d.comb += of.eq(i.of)
# normalisation increase/decrease conditions
decrease = Signal(reset_less=True)
increase = Signal(reset_less=True)
temp_s.eq(temp_m << clz), # shift mantissa UP
self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
- self.o.of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ of.m0.eq(temp_s[2]), # copy of mantissa[0]
# overflow in bits 0..1: got shifted too (leave sticky)
- self.o.of.guard.eq(temp_s[1]), # guard
- self.o.of.round_bit.eq(temp_s[0]), # round
+ of.guard.eq(temp_s[1]), # guard
+ of.round_bit.eq(temp_s[0]), # round
]
# increase exponent
with m.Elif(increase):
msr.inp.eq(temp_m),
msr.diff.eq(ediff_n126),
self.o.z.m.eq(msr.m[3:]),
- self.o.of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ of.m0.eq(temp_s[3]), # copy of mantissa[0]
# overflow in bits 0..1: got shifted too (leave sticky)
- self.o.of.guard.eq(temp_s[2]), # guard
- self.o.of.round_bit.eq(temp_s[1]), # round
- self.o.of.sticky.eq(temp_s[0]), # sticky
+ of.guard.eq(temp_s[2]), # guard
+ of.round_bit.eq(temp_s[1]), # round
+ of.sticky.eq(temp_s[0]), # sticky
self.o.z.e.eq(i.z.e + ediff_n126),
]
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
self.mod = FPNorm1ModSingle(width)
- self.out_norm = Signal(reset_less=True)
- self.out_z = FPNumBase(width)
+ self.out_z = FPNumBase(width, False)
self.out_roundz = Signal(reset_less=True)
def setup(self, m, in_z, in_of, in_mid):
# Normalisation (chained to input in_z+in_of)
nmod = FPNorm1ModSingle(self.width)
- n_out_z = FPNumBase(self.width)
- n_out_roundz = Signal(reset_less=True)
- nmod.setup(m, in_z, in_of, n_out_z)
+ n_out = nmod.ospec()
+ nmod.setup(m, in_z, in_of, n_out.z)
+ m.d.comb += n_out.roundz.eq(nmod.o.roundz)
# Rounding (chained to normalisation)
rmod = FPRoundMod(self.width)
- r_out_z = FPNumBase(self.width)
- rmod.setup(m, n_out_z, n_out_roundz)
- m.d.comb += n_out_roundz.eq(nmod.o.of.roundz)
+ r_out_z = rmod.ospec()
+ rmod.setup(m, n_out.z, n_out.roundz)
m.d.comb += r_out_z.eq(rmod.out_z)
# Corrections (chained to rounding)
cmod = FPCorrectionsMod(self.width)
- c_out_z = FPNumBase(self.width)
+ c_out_z = cmod.ospec()
cmod.setup(m, r_out_z)
m.d.comb += c_out_z.eq(cmod.out_z)
# Pack (chained to corrections)
self.pmod = FPPackMod(self.width)
- self.out_z = FPNumBase(self.width)
+ self.out_z = self.pmod.ospec()
self.pmod.setup(m, c_out_z)
# Multiplex ID
class FPRoundMod:
def __init__(self, width):
- self.in_roundz = Signal(reset_less=True)
- self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
+ self.width = width
+ self.i = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNorm1Data(self.width)
+
+ def ospec(self):
+ return FPNumBase(self.width, False)
def setup(self, m, in_z, roundz):
m.submodules.roundz = self
- m.d.comb += self.in_z.eq(in_z)
- m.d.comb += self.in_roundz.eq(roundz)
+ m.d.comb += self.i.z.eq(in_z)
+ m.d.comb += self.i.roundz.eq(roundz)
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_z.eq(self.in_z)
- with m.If(self.in_roundz):
- m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
- with m.If(self.in_z.m == self.in_z.m1s): # all 1s
- m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+ m.d.comb += self.out_z.eq(self.i.z)
+ with m.If(self.i.roundz):
+ m.d.comb += self.out_z.m.eq(self.i.z.m + 1) # mantissa rounds up
+ with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+ m.d.comb += self.out_z.e.eq(self.i.z.e + 1) # exponent up
return m
FPState.__init__(self, "round")
FPID.__init__(self, id_wid)
self.mod = FPRoundMod(width)
- self.out_z = FPNumBase(width)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
class FPCorrectionsMod:
def __init__(self, width):
- self.in_z = FPNumOut(width, False)
- self.out_z = FPNumOut(width, False)
+ self.width = width
+ self.in_z = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNumOut(self.width, False)
+
+ def ospec(self):
+ return FPNumOut(self.width, False)
def setup(self, m, in_z):
""" links module to inputs and outputs
FPState.__init__(self, "corrections")
FPID.__init__(self, id_wid)
self.mod = FPCorrectionsMod(width)
- self.out_z = FPNumBase(width)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
class FPPackMod:
def __init__(self, width):
- self.in_z = FPNumOut(width, False)
- self.out_z = FPNumOut(width, False)
+ self.width = width
+ self.in_z = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNumOut(self.width, False)
+
+ def ospec(self):
+ return FPNumOut(self.width, False)
def setup(self, m, in_z):
""" links module to inputs and outputs
FPState.__init__(self, "pack")
FPID.__init__(self, id_wid)
self.mod = FPPackMod(width)
- self.out_z = FPNumOut(width, False)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
projects / ieee754fpu.git / blobdiff