self.o = self.mod.ospec()
self.a0mod = FPAddStage0Mod(width)
- self.a0_out_z = FPNumBase(width, False)
- self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
- self.a0_out_z = FPNumBase(width, False)
+ self.a0o = self.a0mod.ospec()
self.a1mod = FPAddStage1Mod(width)
- self.out_z = FPNumBase(width, False)
- self.out_of = Overflow()
+ self.a1o = self.a1mod.ospec()
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
m.d.comb += self.o.eq(self.mod.o)
self.a0mod.setup(m, self.o.a, self.o.b)
- m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
- m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
+ m.d.comb += self.a0o.eq(self.a0mod.o)
- self.a1mod.setup(m, self.out_tot, self.a0_out_z)
+ self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
if self.in_mid is not None:
m.d.comb += self.in_mid.eq(in_mid)
def action(self, m):
self.idsync(m)
- m.d.sync += self.out_of.eq(self.a1mod.out_of)
- m.d.sync += self.out_z.eq(self.a1mod.out_z)
+ m.d.sync += self.a1o.eq(self.a1mod.o)
m.next = "normalise_1"
-class FPAddStage0:
+class FPAddStage0Data:
def __init__(self, width):
- self.out_z = FPNumBase(width, False)
- self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ self.z = FPNumBase(width, False)
+ self.tot = Signal(self.z.m_width + 4, reset_less=True)
def eq(self, i):
- return [self.out_z.eq(i.out_z), self.out_tot.eq(i.out_tot)]
+ return [self.z.eq(i.z), self.tot.eq(i.tot)]
class FPAddStage0Mod:
def __init__(self, width):
self.width = width
self.i = self.ispec()
- self.out_z = FPNumBase(width, False)
- self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ self.o = self.ospec()
def ispec(self):
return FPNumBase2Ops(self.width)
+ def ospec(self):
+ return FPAddStage0Data(self.width)
+
def setup(self, m, in_a, in_b):
""" links module to inputs and outputs
"""
m = Module()
m.submodules.add0_in_a = self.i.a
m.submodules.add0_in_b = self.i.b
- m.submodules.add0_out_z = self.out_z
+ m.submodules.add0_out_z = self.o.z
- m.d.comb += self.out_z.e.eq(self.i.a.e)
+ m.d.comb += self.o.z.e.eq(self.i.a.e)
# store intermediate tests (and zero-extended mantissas)
seq = Signal(reset_less=True)
# same-sign (both negative or both positive) add mantissas
with m.If(seq):
m.d.comb += [
- self.out_tot.eq(am0 + bm0),
- self.out_z.s.eq(self.i.a.s)
+ self.o.tot.eq(am0 + bm0),
+ self.o.z.s.eq(self.i.a.s)
]
# a mantissa greater than b, use a
with m.Elif(mge):
m.d.comb += [
- self.out_tot.eq(am0 - bm0),
- self.out_z.s.eq(self.i.a.s)
+ self.o.tot.eq(am0 - bm0),
+ self.o.z.s.eq(self.i.a.s)
]
# b mantissa greater than a, use b
with m.Else():
m.d.comb += [
- self.out_tot.eq(bm0 - am0),
- self.out_z.s.eq(self.i.b.s)
+ self.o.tot.eq(bm0 - am0),
+ self.o.z.s.eq(self.i.b.s)
]
return m
FPState.__init__(self, "add_0")
FPID.__init__(self, id_wid)
self.mod = FPAddStage0Mod(width)
- self.out_z = FPNumBase(width, False)
- self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+ self.o = self.mod.ospec()
def setup(self, m, in_a, in_b, in_mid):
""" links module to inputs and outputs
def action(self, m):
self.idsync(m)
# NOTE: these could be done as combinatorial (merge add0+add1)
- m.d.sync += self.out_z.eq(self.mod.out_z)
- m.d.sync += self.out_tot.eq(self.mod.out_tot)
+ m.d.sync += self.o.eq(self.mod.o)
m.next = "add_1"
+class FPAddStage1Data:
+
+ def __init__(self, width):
+ self.z = FPNumBase(width, False)
+ self.of = Overflow()
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.of.eq(i.of)]
+
+
+
class FPAddStage1Mod(FPState):
""" Second stage of add: preparation for normalisation.
detects when tot sum is too big (tot[27] is kinda a carry bit)
"""
def __init__(self, width):
- self.out_norm = Signal(reset_less=True)
- self.in_z = FPNumBase(width, False)
- self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
- self.out_z = FPNumBase(width, False)
- self.out_of = Overflow()
+ self.width = width
+ self.i = self.ispec()
+ self.o = self.ospec()
+
+ def ispec(self):
+ return FPAddStage0Data(self.width)
+
+ def ospec(self):
+ return FPAddStage1Data(self.width)
def setup(self, m, in_tot, in_z):
""" links module to inputs and outputs
"""
m.submodules.add1 = self
- m.submodules.add1_out_overflow = self.out_of
+ m.submodules.add1_out_overflow = self.o.of
- m.d.comb += self.in_z.eq(in_z)
- m.d.comb += self.in_tot.eq(in_tot)
+ m.d.comb += self.i.z.eq(in_z)
+ m.d.comb += self.i.tot.eq(in_tot)
def elaborate(self, platform):
m = Module()
#m.submodules.norm1_out_overflow = self.out_of
#m.submodules.norm1_in_z = self.in_z
#m.submodules.norm1_out_z = self.out_z
- m.d.comb += self.out_z.eq(self.in_z)
+ m.d.comb += self.o.z.eq(self.i.z)
# tot[-1] (MSB) gets set when the sum overflows. shift result down
- with m.If(self.in_tot[-1]):
+ with m.If(self.i.tot[-1]):
m.d.comb += [
- self.out_z.m.eq(self.in_tot[4:]),
- self.out_of.m0.eq(self.in_tot[4]),
- self.out_of.guard.eq(self.in_tot[3]),
- self.out_of.round_bit.eq(self.in_tot[2]),
- self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
- self.out_z.e.eq(self.in_z.e + 1)
+ self.o.z.m.eq(self.i.tot[4:]),
+ self.o.of.m0.eq(self.i.tot[4]),
+ self.o.of.guard.eq(self.i.tot[3]),
+ self.o.of.round_bit.eq(self.i.tot[2]),
+ self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
+ self.o.z.e.eq(self.i.z.e + 1)
]
# tot[-1] (MSB) zero case
with m.Else():
m.d.comb += [
- self.out_z.m.eq(self.in_tot[3:]),
- self.out_of.m0.eq(self.in_tot[3]),
- self.out_of.guard.eq(self.in_tot[2]),
- self.out_of.round_bit.eq(self.in_tot[1]),
- self.out_of.sticky.eq(self.in_tot[0])
+ self.o.z.m.eq(self.i.tot[3:]),
+ self.o.of.m0.eq(self.i.tot[3]),
+ self.o.of.guard.eq(self.i.tot[2]),
+ self.o.of.round_bit.eq(self.i.tot[1]),
+ self.o.of.sticky.eq(self.i.tot[0])
]
return m
def __init__(self, width):
self.width = width
- self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
+ self.in_z = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNumBase(self.width, False)
- def setup(self, m, in_z, out_z, modname):
+ def ospec(self):
+ return FPNumBase(self.width, False)
+
+ def setup(self, m, in_z, out_z):
""" links module to inputs and outputs
"""
m.submodules.normalise = self
# initialise out from in (overridden below)
m.d.comb += self.out_z.eq(in_z)
m.d.comb += self.out_of.eq(in_of)
- # normalisation increase/decrease conditions
+ # normalisation decrease condition
decrease = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero)
# decrease exponent
return m
+class FPNorm1Data:
+
+ def __init__(self, width):
+
+ self.roundz = Signal(reset_less=True)
+ self.z = FPNumBase(width, False)
+
+ def eq(self, i):
+ return [self.z.eq(i.z), self.roundz.eq(i.roundz)]
+
class FPNorm1ModSingle:
def __init__(self, width):
self.width = width
- self.out_norm = Signal(reset_less=True)
- self.in_z = FPNumBase(width, False)
- self.in_of = Overflow()
- self.out_z = FPNumBase(width, False)
- self.out_of = Overflow()
+ self.i = self.ispec()
+ self.o = self.ispec()
+
+ def ispec(self):
+ return FPAddStage1Data(self.width)
+
+ def ospec(self):
+ return FPAddStage1Data(self.width) # XXX TODO: FPNorm1Data
def setup(self, m, in_z, in_of, out_z):
""" links module to inputs and outputs
"""
m.submodules.normalise_1 = self
- m.d.comb += self.in_z.eq(in_z)
- m.d.comb += self.in_of.eq(in_of)
+ m.d.comb += self.i.z.eq(in_z)
+ m.d.comb += self.i.of.eq(in_of)
- m.d.comb += out_z.eq(self.out_z)
+ m.d.comb += out_z.eq(self.o.z)
def elaborate(self, platform):
m = Module()
- mwid = self.out_z.m_width+2
+ mwid = self.o.z.m_width+2
pe = PriorityEncoder(mwid)
m.submodules.norm_pe = pe
- m.submodules.norm1_out_z = self.out_z
- m.submodules.norm1_out_overflow = self.out_of
- m.submodules.norm1_in_z = self.in_z
- m.submodules.norm1_in_overflow = self.in_of
+ m.submodules.norm1_out_z = self.o.z
+ m.submodules.norm1_out_overflow = self.o.of
+ m.submodules.norm1_in_z = self.i.z
+ m.submodules.norm1_in_overflow = self.i.of
- in_z = FPNumBase(self.width, False)
- in_of = Overflow()
- m.submodules.norm1_insel_z = in_z
- m.submodules.norm1_insel_overflow = in_of
+ i = self.ispec()
+ m.submodules.norm1_insel_z = i.z
+ m.submodules.norm1_insel_overflow = i.of
- espec = (len(in_z.e), True)
+ espec = (len(i.z.e), True)
ediff_n126 = Signal(espec, reset_less=True)
msr = MultiShiftRMerge(mwid, espec)
m.submodules.multishift_r = msr
- m.d.comb += in_z.eq(self.in_z)
- m.d.comb += in_of.eq(self.in_of)
+ m.d.comb += i.eq(self.i)
# initialise out from in (overridden below)
- m.d.comb += self.out_z.eq(in_z)
- m.d.comb += self.out_of.eq(in_of)
+ m.d.comb += self.o.eq(i)
# normalisation increase/decrease conditions
decrease = Signal(reset_less=True)
increase = Signal(reset_less=True)
- m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
- m.d.comb += increase.eq(in_z.exp_lt_n126)
+ m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
+ m.d.comb += increase.eq(i.z.exp_lt_n126)
# decrease exponent
with m.If(decrease):
# *sigh* not entirely obvious: count leading zeros (clz)
# we reverse the order of the bits.
temp_m = Signal(mwid, reset_less=True)
temp_s = Signal(mwid+1, reset_less=True)
- clz = Signal((len(in_z.e), True), reset_less=True)
+ clz = Signal((len(i.z.e), True), reset_less=True)
# make sure that the amount to decrease by does NOT
# go below the minimum non-INF/NaN exponent
- limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
- in_z.exp_sub_n126)
+ limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
+ i.z.exp_sub_n126)
m.d.comb += [
# cat round and guard bits back into the mantissa
- temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+ temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
pe.i.eq(temp_m[::-1]), # inverted
clz.eq(limclz), # count zeros from MSB down
temp_s.eq(temp_m << clz), # shift mantissa UP
- self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
- self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
- self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
+ self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
+ self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
+ self.o.of.m0.eq(temp_s[2]), # copy of mantissa[0]
# overflow in bits 0..1: got shifted too (leave sticky)
- self.out_of.guard.eq(temp_s[1]), # guard
- self.out_of.round_bit.eq(temp_s[0]), # round
+ self.o.of.guard.eq(temp_s[1]), # guard
+ self.o.of.round_bit.eq(temp_s[0]), # round
]
# increase exponent
with m.Elif(increase):
temp_m = Signal(mwid+1, reset_less=True)
m.d.comb += [
- temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
- in_z.m)),
- ediff_n126.eq(in_z.N126 - in_z.e),
+ temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ i.z.m)),
+ ediff_n126.eq(i.z.N126 - i.z.e),
# connect multi-shifter to inp/out mantissa (and ediff)
msr.inp.eq(temp_m),
msr.diff.eq(ediff_n126),
- self.out_z.m.eq(msr.m[3:]),
- self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
+ self.o.z.m.eq(msr.m[3:]),
+ self.o.of.m0.eq(temp_s[3]), # copy of mantissa[0]
# overflow in bits 0..1: got shifted too (leave sticky)
- self.out_of.guard.eq(temp_s[2]), # guard
- self.out_of.round_bit.eq(temp_s[1]), # round
- self.out_of.sticky.eq(temp_s[0]), # sticky
- self.out_z.e.eq(in_z.e + ediff_n126),
+ self.o.of.guard.eq(temp_s[2]), # guard
+ self.o.of.round_bit.eq(temp_s[1]), # round
+ self.o.of.sticky.eq(temp_s[0]), # sticky
+ self.o.z.e.eq(i.z.e + ediff_n126),
]
return m
def __init__(self, width, single_cycle=True):
self.width = width
self.in_select = Signal(reset_less=True)
- self.out_norm = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
self.in_of = Overflow()
self.temp_z = FPNumBase(width, False)
FPID.__init__(self, id_wid)
FPState.__init__(self, "normalise_1")
self.mod = FPNorm1ModSingle(width)
- self.out_norm = Signal(reset_less=True)
- self.out_z = FPNumBase(width)
+ self.out_z = FPNumBase(width, False)
self.out_roundz = Signal(reset_less=True)
def setup(self, m, in_z, in_of, in_mid):
# Rounding (chained to normalisation)
rmod = FPRoundMod(self.width)
- r_out_z = FPNumBase(self.width)
+ r_out_z = rmod.ospec()
rmod.setup(m, n_out_z, n_out_roundz)
- m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
+ m.d.comb += n_out_roundz.eq(nmod.o.of.roundz)
m.d.comb += r_out_z.eq(rmod.out_z)
# Corrections (chained to rounding)
cmod = FPCorrectionsMod(self.width)
- c_out_z = FPNumBase(self.width)
+ c_out_z = cmod.ospec()
cmod.setup(m, r_out_z)
m.d.comb += c_out_z.eq(cmod.out_z)
# Pack (chained to corrections)
self.pmod = FPPackMod(self.width)
- self.out_z = FPNumBase(self.width)
+ self.out_z = self.pmod.ospec()
self.pmod.setup(m, c_out_z)
# Multiplex ID
class FPRoundMod:
def __init__(self, width):
- self.in_roundz = Signal(reset_less=True)
- self.in_z = FPNumBase(width, False)
- self.out_z = FPNumBase(width, False)
+ self.width = width
+ self.i = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNorm1Data(self.width)
+
+ def ospec(self):
+ return FPNumBase(self.width, False)
def setup(self, m, in_z, roundz):
m.submodules.roundz = self
- m.d.comb += self.in_z.eq(in_z)
- m.d.comb += self.in_roundz.eq(roundz)
+ m.d.comb += self.i.z.eq(in_z)
+ m.d.comb += self.i.roundz.eq(roundz)
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_z.eq(self.in_z)
- with m.If(self.in_roundz):
- m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
- with m.If(self.in_z.m == self.in_z.m1s): # all 1s
- m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+ m.d.comb += self.out_z.eq(self.i.z)
+ with m.If(self.i.roundz):
+ m.d.comb += self.out_z.m.eq(self.i.z.m + 1) # mantissa rounds up
+ with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+ m.d.comb += self.out_z.e.eq(self.i.z.e + 1) # exponent up
return m
FPState.__init__(self, "round")
FPID.__init__(self, id_wid)
self.mod = FPRoundMod(width)
- self.out_z = FPNumBase(width)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, roundz, in_mid):
""" links module to inputs and outputs
class FPCorrectionsMod:
def __init__(self, width):
- self.in_z = FPNumOut(width, False)
- self.out_z = FPNumOut(width, False)
+ self.width = width
+ self.in_z = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNumOut(self.width, False)
+
+ def ospec(self):
+ return FPNumOut(self.width, False)
def setup(self, m, in_z):
""" links module to inputs and outputs
FPState.__init__(self, "corrections")
FPID.__init__(self, id_wid)
self.mod = FPCorrectionsMod(width)
- self.out_z = FPNumBase(width)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
class FPPackMod:
def __init__(self, width):
- self.in_z = FPNumOut(width, False)
- self.out_z = FPNumOut(width, False)
+ self.width = width
+ self.in_z = self.ispec()
+ self.out_z = self.ospec()
+
+ def ispec(self):
+ return FPNumOut(self.width, False)
+
+ def ospec(self):
+ return FPNumOut(self.width, False)
def setup(self, m, in_z):
""" links module to inputs and outputs
FPState.__init__(self, "pack")
FPID.__init__(self, id_wid)
self.mod = FPPackMod(width)
- self.out_z = FPNumOut(width, False)
+ self.out_z = self.mod.ospec()
def setup(self, m, in_z, in_mid):
""" links module to inputs and outputs
alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
- n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
+ n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
n1.in_mid, self.out_mid))
projects / ieee754fpu.git / blobdiff