update comments

[ieee754fpu.git] / src / add / nmigen_div_experiment.py

diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index 5dccecb50c350eeef5f1f9bc48922a43fcb0c0fb..a7e215cb888817b750426af676a7825552dee431 100644 (file)
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -43,7 +43,7 @@ class FPDIV(FPBase):
         self.states.append(state)
         return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPDiv
         """
         m = Module()
@@ -71,14 +71,14 @@ class FPDIV(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "get_b")
-                m.d.sync += eq([a, self.in_a.o_ready], res)
+                m.d.sync += eq([a, self.in_a.ready_o], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
                 res = self.get_op(m, self.in_b, b, "special_cases")
-                m.d.sync += eq([b, self.in_b.o_ready], res)
+                m.d.sync += eq([b, self.in_b.ready_o], res)
 
             # ******
             # special cases: NaNs, infs, zeros, denormalised