-# IEEE Floating Point Adder (Single Precision)
+# IEEE Floating Point Divider (Single Precision)
# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Const
+from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
-from fpbase import FPNum, FPOp, Overflow, FPBase
+from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
+from singlepipe import eq
class Div:
def __init__(self, width):
self.width = width
- self.quotient = Signal(width)
- self.divisor = Signal(width)
- self.dividend = Signal(width)
- self.remainder = Signal(width)
- self.count = Signal(6)
+ self.quot = Signal(width) # quotient
+ self.dor = Signal(width) # divisor
+ self.dend = Signal(width) # dividend
+ self.rem = Signal(width) # remainder
+ self.count = Signal(7) # loop count
self.czero = Const(0, width)
def reset(self, m):
m.d.sync += [
- self.quotient.eq(self.czero),
- self.remainder.eq(self.czero),
- self.count.eq(Const(0, 6))
+ self.quot.eq(self.czero),
+ self.rem.eq(self.czero),
+ self.count.eq(Const(0, 7))
]
FPBase.__init__(self)
self.width = width
- self.in_a = FPOp(width)
- self.in_b = FPOp(width)
- self.out_z = FPOp(width)
+ self.in_a = FPOpIn(width)
+ self.in_b = FPOpIn(width)
+ self.out_z = FPOpOut(width)
- def get_fragment(self, platform=None):
- """ creates the HDL code-fragment for FPAdd
+ self.states = []
+
+ def add_state(self, state):
+ self.states.append(state)
+ return state
+
+ def elaborate(self, platform=None):
+ """ creates the HDL code-fragment for FPDiv
"""
m = Module()
# Latches
- a = FPNum(self.width, 24)
- b = FPNum(self.width, 24)
- z = FPNum(self.width, 24)
+ a = FPNumIn(None, self.width, False)
+ b = FPNumIn(None, self.width, False)
+ z = FPNumOut(self.width, False)
- div = Div(50)
+ div = Div(a.m_width*2 + 3) # double the mantissa width plus g/r/sticky
of = Overflow()
+ m.submodules.in_a = a
+ m.submodules.in_b = b
+ m.submodules.z = z
+ m.submodules.of = of
+
+ m.d.comb += a.v.eq(self.in_a.v)
+ m.d.comb += b.v.eq(self.in_b.v)
with m.FSM() as fsm:
# gets operand a
with m.State("get_a"):
- self.get_op(m, self.in_a, a, "get_b")
+ res = self.get_op(m, self.in_a, a, "get_b")
+ m.d.sync += eq([a, self.in_a.ready_o], res)
# ******
# gets operand b
with m.State("get_b"):
- self.get_op(m, self.in_b, b, "special_cases")
+ res = self.get_op(m, self.in_b, b, "special_cases")
+ m.d.sync += eq([b, self.in_b.ready_o], res)
# ******
# special cases: NaNs, infs, zeros, denormalised
- # NOTE: some of these are unique to add. see "Special Operations"
+ # NOTE: some of these are unique to div. see "Special Operations"
# https://steve.hollasch.net/cgindex/coding/ieeefloat.html
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
- with m.If(a.is_nan() | b.is_nan()):
+ with m.If(a.is_nan | b.is_nan):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is Inf and b is Inf return NaN
- with m.Elif(a.is_inf() | b.is_inf()):
+ with m.Elif(a.is_inf & b.is_inf):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN if b is zero)
- with m.Elif(a.is_inf()):
+ with m.Elif(a.is_inf):
m.next = "put_z"
- # if b is zero return NaN
- with m.If(b.is_zero()):
- m.d.sync += z.nan(1)
- with m.Else():
- m.d.sync += z.inf(a.s ^ b.s)
+ m.d.sync += z.inf(a.s ^ b.s)
# if b is inf return zero
- with m.Elif(b.is_inf()):
+ with m.Elif(b.is_inf):
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
- # if a is inf return zero (or NaN if b is zero)
- with m.Elif(a.is_inf()):
+ # if a is zero return zero (or NaN if b is zero)
+ with m.Elif(a.is_zero):
m.next = "put_z"
# if b is zero return NaN
- with m.If(b.is_zero()):
+ with m.If(b.is_zero):
m.d.sync += z.nan(1)
with m.Else():
- m.d.sync += z.inf(a.s ^ b.s)
+ m.d.sync += z.zero(a.s ^ b.s)
# if b is zero return Inf
- with m.Elif(b.is_zero()):
+ with m.Elif(b.is_zero):
m.next = "put_z"
- m.d.sync += z.zero(a.s ^ b.s)
+ m.d.sync += z.inf(a.s ^ b.s)
# Denormalised Number checks
with m.Else():
m.d.sync += [
z.s.eq(a.s ^ b.s), # sign
z.e.eq(a.e - b.e), # exponent
- div.dividend.eq(a.m<<27),
- div.divisor.eq(b.m),
+ div.dend.eq(a.m<<(a.m_width+3)), # 3 bits for g/r/sticky
+ div.dor.eq(b.m),
]
div.reset(m)
with m.State("divide_1"):
m.next = "divide_2"
m.d.sync += [
- div.quotient.eq(div.quotient << 1),
- div.remainder.eq(Cat(dividend[0], div.remainder[2:])),
- div.dividend.eq(div.dividend << 1),
+ div.quot.eq(div.quot << 1),
+ div.rem.eq(Cat(div.dend[-1], div.rem[0:])),
+ div.dend.eq(div.dend << 1),
]
# ******
# Third stage of divide.
+ # This stage ends by jumping out to divide_3
+ # However it defaults to jumping to divide_1 (which comes back here)
with m.State("divide_2"):
- with m.If(div.remainder >= div.divisor):
+ with m.If(div.rem >= div.dor):
m.d.sync += [
- div.quotient[0].eq(1),
- div.remainder.eq(div.remainder - div.divisor),
+ div.quot[0].eq(1),
+ div.rem.eq(div.rem - div.dor),
]
- with m.If(count == div.width-1):
+ with m.If(div.count == div.width-2):
m.next = "divide_3"
with m.Else():
m.next = "divide_1"
with m.State("divide_3"):
m.next = "normalise_1"
m.d.sync += [
- z.m.eq(div.quotient[3:27]),
- of.guard.eq(div.quotient[2]),
- of.round_bit.eq(div.quotient[1]),
- of.sticky.eq(div.quotient[0] | div.remainder != 0)
+ z.m.eq(div.quot[3:]),
+ of.guard.eq(div.quot[2]),
+ of.round_bit.eq(div.quot[1]),
+ of.sticky.eq(div.quot[0] | (div.rem != 0))
]
# ******
# rounding stage
with m.State("round"):
- self.roundz(m, z, of, "corrections")
+ self.roundz(m, z, of.roundz)
+ m.next = "corrections"
# ******
# correction stage
projects / ieee754fpu.git / blobdiff