from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
-from nmigen_add_experiment import FPState
+from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
+from singlepipe import eq
class Div:
def __init__(self, width):
FPBase.__init__(self)
self.width = width
- self.in_a = FPOp(width)
- self.in_b = FPOp(width)
- self.out_z = FPOp(width)
+ self.in_a = FPOpIn(width)
+ self.in_b = FPOpIn(width)
+ self.out_z = FPOpOut(width)
self.states = []
self.states.append(state)
return state
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPDiv
"""
m = Module()
m.submodules.z = z
m.submodules.of = of
+ m.d.comb += a.v.eq(self.in_a.v)
+ m.d.comb += b.v.eq(self.in_b.v)
+
with m.FSM() as fsm:
# ******
# gets operand a
with m.State("get_a"):
- self.get_op(m, self.in_a, a, "get_b")
+ res = self.get_op(m, self.in_a, a, "get_b")
+ m.d.sync += eq([a, self.in_a.ready_o], res)
# ******
# gets operand b
with m.State("get_b"):
- self.get_op(m, self.in_b, b, "special_cases")
+ res = self.get_op(m, self.in_b, b, "special_cases")
+ m.d.sync += eq([b, self.in_b.ready_o], res)
# ******
# special cases: NaNs, infs, zeros, denormalised