update comments

[ieee754fpu.git] / src / add / nmigen_div_experiment.py

diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index ff0e54cba7b96d7e95c90318b3127cf97e693465..a7e215cb888817b750426af676a7825552dee431 100644 (file)
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal, Const, Cat
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
+from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState
 from singlepipe import eq
 
 class Div:
@@ -33,9 +33,9 @@ class FPDIV(FPBase):
         FPBase.__init__(self)
         self.width = width
 
-        self.in_a  = FPOp(width)
-        self.in_b  = FPOp(width)
-        self.out_z = FPOp(width)
+        self.in_a  = FPOpIn(width)
+        self.in_b  = FPOpIn(width)
+        self.out_z = FPOpOut(width)
 
         self.states = []
 
@@ -43,7 +43,7 @@ class FPDIV(FPBase):
         self.states.append(state)
         return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPDiv
         """
         m = Module()
@@ -71,14 +71,14 @@ class FPDIV(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "get_b")
-                m.d.sync += eq([a, self.in_a.ack], res)
+                m.d.sync += eq([a, self.in_a.ready_o], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
                 res = self.get_op(m, self.in_b, b, "special_cases")
-                m.d.sync += eq([b, self.in_b.ack], res)
+                m.d.sync += eq([b, self.in_b.ready_o], res)
 
             # ******
             # special cases: NaNs, infs, zeros, denormalised