update comments

[ieee754fpu.git] / src / add / pipeline.py

diff --git a/src/add/pipeline.py b/src/add/pipeline.py
index 6958c2a254ee5d826334fceff9d1fb93d4b8c131..afcee743982175e31a833a208067bf59ec2c3978 100644 (file)
--- a/src/add/pipeline.py
+++ b/src/add/pipeline.py
@@ -8,7 +8,8 @@ from nmigen import tracer
 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
 from contextlib import contextmanager
 
-from singlepipe import eq, StageCls, ControlBase, BufferedHandshake
+from nmoperator import eq
+from singlepipe import StageCls, ControlBase, BufferedHandshake
 from singlepipe import UnbufferedPipeline
 
 
@@ -130,20 +131,20 @@ class ObjectProxy:
         self._preg_map[name] = new_pipereg
         #object.__setattr__(self, name, new_pipereg)
         if self._pipemode:
-            print ("OP pipemode", self._syncmode, new_pipereg, value)
+            #print ("OP pipemode", self._syncmode, new_pipereg, value)
             assign = eq(new_pipereg, value)
             if self._syncmode:
                 self._m.d.sync += assign
             else:
                 self._m.d.comb += assign
         elif self._m:
-            print ("OP !pipemode assign", new_pipereg, value, type(value))
+            #print ("OP !pipemode assign", new_pipereg, value, type(value))
             self._m.d.comb += eq(new_pipereg, value)
         else:
-            print ("OP !pipemode !m", new_pipereg, value, type(value))
+            #print ("OP !pipemode !m", new_pipereg, value, type(value))
             self._assigns += eq(new_pipereg, value)
             if isinstance(value, ObjectProxy):
-                print ("OP, defer assigns:", value._assigns)
+                #print ("OP, defer assigns:", value._assigns)
                 self._assigns += value._assigns
                 self._eqs.append(value._eqs)