update comments

[ieee754fpu.git] / src / add / record_experiment.py

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 2cbc637ab74f50c9d539ac75da7b99d09be59053..1789c3bd8a6125819153921da42dcf9f6b87a14f 100644 (file)
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -1,4 +1,4 @@
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
 from nmigen.hdl.rec import Record, Layout, DIR_NONE
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
@@ -51,7 +51,7 @@ def testbench(dut):
 
 
 
-class RecordTest2:
+class RecordTest2(Elaboratable):
 
     def __init__(self):
         self.r1 = RecordObject()