update comments

[ieee754fpu.git] / src / add / record_experiment.py

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 6c2545e09b82524d8bf93a5e42b153798db114bb..1789c3bd8a6125819153921da42dcf9f6b87a14f 100644 (file)
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -1,49 +1,34 @@
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
 from nmigen.hdl.rec import Record, Layout, DIR_NONE
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
-from singlepipe import flatten
-
-
-class RecordObject(Record):
-    def __init__(self, name=None):
-        Record.__init__(self, layout=[], name=None)
-
-    def __setattr__(self, k, v):
-        if k in dir(Record) or "fields" not in self.__dict__:
-            return object.__setattr__(self, k, v)
-        self.__dict__["fields"][k] = v
-        if isinstance(v, Record):
-            newlayout = {k: (k, v.layout)}
-        else:
-            newlayout = {k: (k, v.shape())}
-        self.__dict__["layout"].fields.update(newlayout)
+from singlepipe import cat, RecordObject
 
 
 class RecordTest:
 
     def __init__(self):
         self.r1 = RecordObject()
-        self.r1.sig1 = Signal(32)
+        self.r1.sig1 = Signal(16)
         self.r1.r2 = RecordObject()
-        self.r1.r2.sig2 = Signal(32)
+        self.r1.r2.sig2 = Signal(16)
         self.r1.r3 = RecordObject()
-        self.r1.r3.sig3 = Signal(32)
-        self.sig123 = Signal(96)
+        self.r1.r3.sig3 = Signal(16)
+        self.sig123 = Signal(48)
 
     def elaborate(self, platform):
         m = Module()
 
-        sig1 = Signal(32)
+        sig1 = Signal(16)
         m.d.comb += sig1.eq(self.r1.sig1)
-        sig2 = Signal(32)
+        sig2 = Signal(16)
         m.d.comb += sig2.eq(self.r1.r2.sig2)
 
         print (self.r1.fields)
         print (self.r1.shape())
-        print (len(self.r1))
-        m.d.comb += self.sig123.eq(flatten(self.r1))
+        print ("width", len(self.r1))
+        m.d.comb += self.sig123.eq(cat(self.r1))
 
         return m
 
@@ -51,12 +36,53 @@ class RecordTest:
 def testbench(dut):
     yield dut.r1.sig1.eq(5)
     yield dut.r1.r2.sig2.eq(10)
+    yield dut.r1.r3.sig3.eq(1)
     
     sig1 = yield dut.r1.sig1
     assert sig1 == 5
     sig2 = yield dut.r1.r2.sig2
     assert sig2 == 10
 
+    yield
+
+    sig123 = yield dut.sig123
+    print ("sig123", hex(sig123))
+    assert sig123 == 0x1000a0005
+
+
+
+class RecordTest2(Elaboratable):
+
+    def __init__(self):
+        self.r1 = RecordObject()
+        self.r1.sig1 = Signal(16)
+        self.r1.r2 = RecordObject()
+        self.r1.r2.sig2 = Signal(16)
+        self.r1.r3 = RecordObject()
+        self.r1.r3.sig3 = Signal(16)
+        self.sig123 = Signal(48)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += cat(self.r1).eq(self.sig123)
+
+        return m
+
+
+def testbench2(dut):
+    
+    sig123 = yield dut.sig123.eq(0x1000a0005)
+
+    yield
+
+    sig1 = yield dut.r1.sig1
+    assert sig1 == 5
+    sig2 = yield dut.r1.r2.sig2
+    assert sig2 == 10
+    sig3 = yield dut.r1.r3.sig3
+    assert sig3 == 1
+
 
 
 ######################################################################
@@ -71,3 +97,10 @@ if __name__ == '__main__':
     with open("test_record1.il", "w") as f:
         f.write(vl)
 
+    print ("test 2")
+    dut = RecordTest2()
+    run_simulation(dut, testbench2(dut), vcd_name="test_record2.vcd")
+    vl = rtlil.convert(dut, ports=[dut.sig123, dut.r1.sig1, dut.r1.r2.sig2])
+    with open("test_record2.il", "w") as f:
+        f.write(vl)
+