update comments

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 892e3ace59ac3f7ce236696417d3cb1d37e2d226..37f2b31f8b0a3ce38d2067b569a28344e6ab7fd9 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -480,6 +480,7 @@ class ExampleAddRecordPlaceHolderStage(StageCls):
         return o
 
 
+# a dummy class that may have stuff assigned to instances once created
 class PlaceHolder: pass
 
 
@@ -547,7 +548,7 @@ class ExampleAddClassStage(StageCls):
         """ returns an output signal which will happen to contain the sum
             of the two inputs
         """
-        return Signal(16)
+        return Signal(16, name="add2_out")
 
     def process(self, i):
         """ process the input data (sums the values in the tuple) and returns it
@@ -789,12 +790,14 @@ class ExampleFIFOPassThruPipe1(ControlBase):
         m = ControlBase.elaborate(self, platform)
 
         pipe1 = FIFOTest16()
-        pipe2 = ExamplePassAdd1Pipe()
+        pipe2 = FIFOTest16()
+        pipe3 = ExamplePassAdd1Pipe()
 
         m.submodules.pipe1 = pipe1
         m.submodules.pipe2 = pipe2
+        m.submodules.pipe3 = pipe3
 
-        m.d.comb += self.connect([pipe1, pipe2])
+        m.d.comb += self.connect([pipe1, pipe2, pipe3])
 
         return m