rename p.data to p.i_data and n.data to n.o_data

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 76c71a8332f44142cf518c3200536b2b817160ac..b84a66042607551e122d3569d1f5e94f12aa27dc 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -19,24 +19,24 @@ def testbench(dut):
     yield
     #yield dut.i_p_rst.eq(0)
     yield dut.n.i_ready.eq(1)
-    yield dut.p.data.eq(5)
+    yield dut.p.i_data.eq(5)
     yield dut.p.i_valid.eq(1)
     yield
 
-    yield dut.p.data.eq(7)
+    yield dut.p.i_data.eq(7)
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
     yield
     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
 
-    yield dut.p.data.eq(2)
+    yield dut.p.i_data.eq(2)
     yield
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
-    yield dut.p.data.eq(9)
+    yield dut.p.i_data.eq(9)
     yield
     yield dut.p.i_valid.eq(0)
-    yield dut.p.data.eq(12)
+    yield dut.p.i_data.eq(12)
     yield
-    yield dut.p.data.eq(32)
+    yield dut.p.i_data.eq(32)
     yield dut.n.i_ready.eq(1)
     yield
     yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@ -55,25 +55,25 @@ def testbench2(dut):
     yield
     #yield dut.p.i_rst.eq(0)
     yield dut.n.i_ready.eq(1)
-    yield dut.p.data.eq(5)
+    yield dut.p.i_data.eq(5)
     yield dut.p.i_valid.eq(1)
     yield
 
-    yield dut.p.data.eq(7)
+    yield dut.p.i_data.eq(7)
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
     yield
     yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
 
-    yield dut.p.data.eq(2)
+    yield dut.p.i_data.eq(2)
     yield
     yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
     yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
-    yield dut.p.data.eq(9)
+    yield dut.p.i_data.eq(9)
     yield
     yield dut.p.i_valid.eq(0)
-    yield dut.p.data.eq(12)
+    yield dut.p.i_data.eq(12)
     yield
-    yield dut.p.data.eq(32)
+    yield dut.p.i_data.eq(32)
     yield dut.n.i_ready.eq(1)
     yield
     yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@ -113,7 +113,7 @@ class Test3:
                     continue
                 if send and self.i != len(self.data):
                     yield self.dut.p.i_valid.eq(1)
-                    yield self.dut.p.data.eq(self.data[self.i])
+                    yield self.dut.p.i_data.eq(self.data[self.i])
                     self.i += 1
                 else:
                     yield self.dut.p.i_valid.eq(0)
@@ -130,7 +130,7 @@ class Test3:
                 i_n_ready = yield self.dut.n.i_ready
                 if not o_n_valid or not i_n_ready:
                     continue
-                o_data = yield self.dut.n.data
+                o_data = yield self.dut.n.o_data
                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
                 self.o += 1
                 if self.o == len(self.data):
@@ -183,7 +183,7 @@ class Test5:
                 i_n_ready = yield self.dut.n.i_ready
                 if not o_n_valid or not i_n_ready:
                     continue
-                o_data = yield self.dut.n.data
+                o_data = yield self.dut.n.o_data
                 self.resultfn(o_data, self.data[self.o], self.i, self.o)
                 self.o += 1
                 if self.o == len(self.data):
@@ -210,7 +210,7 @@ def testbench4(dut):
         if o_p_ready:
             if send and i != len(data):
                 yield dut.p.i_valid.eq(1)
-                yield dut.p.data.eq(data[i])
+                yield dut.p.i_data.eq(data[i])
                 i += 1
             else:
                 yield dut.p.i_valid.eq(0)
@@ -218,7 +218,7 @@ def testbench4(dut):
         o_n_valid = yield dut.n.o_valid
         i_n_ready = yield dut.n.i_ready
         if o_n_valid and i_n_ready:
-            o_data = yield dut.n.data
+            o_data = yield dut.n.o_data
             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
                                         % (i, o, o_data, data[o])
             o += 1
@@ -232,7 +232,7 @@ class ExampleBufPipe2:
                               v               v
         i_p_valid >>in  pipe1 o_n_valid out>> i_p_valid >>in  pipe2
         o_p_ready <<out pipe1 i_n_ready <<in  o_p_ready <<out pipe2
-        p_data    >>in  pipe1 o_data    out>> p_data    >>in  pipe2
+        p_i_data  >>in  pipe1 p_i_data  out>> n_o_data  >>in  pipe2
     """
     def __init__(self):
         self.pipe1 = ExampleBufPipe()
@@ -240,11 +240,11 @@ class ExampleBufPipe2:
 
         # input
         self.p = PrevControl()
-        self.p.data = Signal(32) # >>in - comes in from the PREVIOUS stage
+        self.p.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
 
         # output
         self.n = NextControl()
-        self.n.data = Signal(32) # out>> - goes out to the NEXT stage
+        self.n.o_data = Signal(32) # out>> - goes out to the NEXT stage
 
     def elaborate(self, platform):
         m = Module()
@@ -252,7 +252,7 @@ class ExampleBufPipe2:
         m.submodules.pipe2 = self.pipe2
 
         # connect inter-pipe input/output valid/ready/data
-        m.d.comb += self.pipe1.connect_next(self.pipe2)
+        m.d.comb += self.pipe1.connect_to_next(self.pipe2)
 
         # inputs/outputs to the module: pipe1 connections here (LHS)
         m.d.comb += self.pipe1.connect_in(self)