create classes for STB/BUSY, split in from out

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 8590ccadb8331c29488aa644352a6d13120cd45e..baa344a91faa442b4b93d87d878f9db687ca3152 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -5,20 +5,24 @@ from random import randint
 
 
 def check_o_n_stb(dut, val):
+    o_n_stb = yield dut.o.n_stb
+    assert o_n_stb == val
+
+def check_o_n_stb2(dut, val):
     o_n_stb = yield dut.o_n_stb
     assert o_n_stb == val
 
 
 def testbench(dut):
     #yield dut.i_p_rst.eq(1)
-    yield dut.i_n_busy.eq(1)
-    yield dut.o_p_busy.eq(1)
+    yield dut.i.n_busy.eq(1)
+    yield dut.o.p_busy.eq(1)
     yield
     yield
     #yield dut.i_p_rst.eq(0)
-    yield dut.i_n_busy.eq(0)
+    yield dut.i.n_busy.eq(0)
     yield dut.stage.i_data.eq(5)
-    yield dut.i_p_stb.eq(1)
+    yield dut.i.p_stb.eq(1)
     yield
 
     yield dut.stage.i_data.eq(7)
@@ -28,14 +32,14 @@ def testbench(dut):
 
     yield dut.stage.i_data.eq(2)
     yield
-    yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
+    yield dut.i.n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.stage.i_data.eq(9)
     yield
-    yield dut.i_p_stb.eq(0)
+    yield dut.i.p_stb.eq(0)
     yield dut.stage.i_data.eq(12)
     yield
     yield dut.stage.i_data.eq(32)
-    yield dut.i_n_busy.eq(0)
+    yield dut.i.n_busy.eq(0)
     yield
     yield from check_o_n_stb(dut, 1) # buffer still needs to output
     yield
@@ -46,25 +50,25 @@ def testbench(dut):
 
 
 def testbench2(dut):
-    #yield dut.i_p_rst.eq(1)
+    #yield dut.i.p_rst.eq(1)
     yield dut.i_n_busy.eq(1)
-    #yield dut.o_p_busy.eq(1)
+    #yield dut.o.p_busy.eq(1)
     yield
     yield
-    #yield dut.i_p_rst.eq(0)
+    #yield dut.i.p_rst.eq(0)
     yield dut.i_n_busy.eq(0)
     yield dut.i_data.eq(5)
     yield dut.i_p_stb.eq(1)
     yield
 
     yield dut.i_data.eq(7)
-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
     yield
-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
 
     yield dut.i_data.eq(2)
     yield
-    yield from check_o_n_stb(dut, 1) # ok *now* i_p_stb effect is felt
+    yield from check_o_n_stb2(dut, 1) # ok *now* i_p_stb effect is felt
     yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.i_data.eq(9)
     yield
@@ -74,13 +78,13 @@ def testbench2(dut):
     yield dut.i_data.eq(32)
     yield dut.i_n_busy.eq(0)
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
+    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb(dut, 0) # buffer outputted, *now* we're done.
+    yield from check_o_n_stb2(dut, 0) # buffer outputted, *now* we're done.
     yield
     yield
     yield
@@ -104,16 +108,16 @@ class Test3:
                     send = True
                 else:
                     send = randint(0, send_range) != 0
-                o_p_busy = yield self.dut.o_p_busy
+                o_p_busy = yield self.dut.o.p_busy
                 if o_p_busy:
                     yield
                     continue
                 if send and self.i != len(self.data):
-                    yield self.dut.i_p_stb.eq(1)
+                    yield self.dut.i.p_stb.eq(1)
                     yield self.dut.stage.i_data.eq(self.data[self.i])
                     self.i += 1
                 else:
-                    yield self.dut.i_p_stb.eq(0)
+                    yield self.dut.i.p_stb.eq(0)
                 yield
 
     def rcv(self):
@@ -121,10 +125,10 @@ class Test3:
             stall_range = randint(0, 3)
             for j in range(randint(1,10)):
                 stall = randint(0, stall_range) == 0
-                yield self.dut.i_n_busy.eq(stall)
+                yield self.dut.i.n_busy.eq(stall)
                 yield
-                o_n_stb = yield self.dut.o_n_stb
-                i_n_busy = yield self.dut.i_n_busy
+                o_n_stb = yield self.dut.o.n_stb
+                i_n_busy = yield self.dut.i.n_busy
                 if not o_n_stb or i_n_busy:
                     continue
                 o_data = yield self.dut.stage.o_data
@@ -195,18 +199,18 @@ class BufPipe2:
         m.submodules.pipe2 = self.pipe2
 
         # connect inter-pipe input/output stb/busy/data
-        m.d.comb += self.pipe2.i_p_stb.eq(self.pipe1.o_n_stb)
-        m.d.comb += self.pipe1.i_n_busy.eq(self.pipe2.o_p_busy)
+        m.d.comb += self.pipe2.i.p_stb.eq(self.pipe1.o.n_stb)
+        m.d.comb += self.pipe1.i.n_busy.eq(self.pipe2.o.p_busy)
         m.d.comb += self.pipe2.stage.i_data.eq(self.pipe1.stage.o_data)
 
         # inputs/outputs to the module: pipe1 connections here (LHS)
-        m.d.comb += self.pipe1.i_p_stb.eq(self.i_p_stb)
-        m.d.comb += self.o_p_busy.eq(self.pipe1.o_p_busy)
+        m.d.comb += self.pipe1.i.p_stb.eq(self.i_p_stb)
+        m.d.comb += self.o_p_busy.eq(self.pipe1.o.p_busy)
         m.d.comb += self.pipe1.stage.i_data.eq(self.i_data)
 
         # now pipe2 connections (RHS)
-        m.d.comb += self.o_n_stb.eq(self.pipe2.o_n_stb)
-        m.d.comb += self.pipe2.i_n_busy.eq(self.i_n_busy)
+        m.d.comb += self.o_n_stb.eq(self.pipe2.o.n_stb)
+        m.d.comb += self.pipe2.i.n_busy.eq(self.i_n_busy)
         m.d.comb += self.o_data.eq(self.pipe2.stage.o_data)
 
         return m